Memory controller, semiconductor memory device, and control method for semiconductor memory device

Patent metadata

Field	Value
Publication number	US-2016285478-A1
Application number	US-201514847607-A
Country	US
Kind code	A1
Filing date	Sep 8, 2015
Priority date	Mar 27, 2015
Publication date	Sep 29, 2016
Grant date	—

Abstract

A memory controller is a memory controller including an encoder that product-codes, with a linear code, data to be recorded in a memory section and a decoder that decodes product-coded data read out from the memory section. The encoder and the decoder share a parity generation circuit including a plurality of remainder calculating and retaining sections, each including a remainder calculation circuit by a generator polynomial and a retaining circuit that retains an output of the remainder calculation circuit.

First claim

What is claimed is:

1 . A memory controller comprising:
an encoder that product-codes, with a linear code, data to be recorded in a memory section; and a decoder that decodes product-coded data read out from the memory section, wherein the encoder and the decoder share a common parity generation circuit including a plurality of remainder calculating and retaining sections, each including a remainder calculation circuit by a generator polynomial and a retaining circuit that retains an output of the remainder calculation circuit.

2 . The memory controller according to claim 1 , wherein the product code is a two-dimensional product code by a first code and a second code.

3 . The memory controller according to claim 2 , comprising:
a first parity generation circuit including the remainder calculating and retaining section that performs coding processing by the first code and generates a parity of the first code; and a second parity generation circuit that performs coding processing by the second code and generates a parity of the second code, wherein the second parity generation circuit is the common parity generation circuit, the coding processing by the second code is performed together with the coding processing by the first code, the parity of the second code is retained in the retaining circuit, decoding processing by the second code is performed together with decoding processing by the first code, and the decoder includes a syndrome generation circuit that divides the parity of the second code retained in the retaining circuit by a minimal polynomial of the generator polynomial.

4 . The memory controller according to claim 3 , wherein the encoder and the decoder further share the first parity generation circuit.

5 . The memory controller according to claim 3 , wherein
the remainder calculation circuit is a linear feedback register, and the retaining circuit is a flip-flop.

6 . The memory controller according to claim 3 , wherein the first code and the second code are BCH codes.

7 . The memory controller according to claim 3 , wherein the first code is a BCH code and the second code is a Reed Solomon code.

8 . The memory controller according to claim 3 , wherein the memory section is a NAND flash memory, a NOR flash memory, a magnetoresistive random access memory, or a resistive random access memory.

9 . The memory controller according to claim 8 , wherein a memory cell of the memory section is a multi-value memory.

10 . A semiconductor memory device comprising:
a memory section; and a memory controller including an encoder that product-codes, with a linear code, data to be recorded in the memory section and a decoder that decodes product-coded data read out from the memory section, wherein the encoder and the decoder share a parity generation circuit including a plurality of remainder calculating and retaining sections, each including a remainder calculation circuit by a generator polynomial and a retaining circuit that retains an output of the remainder calculation circuit.

11 . The semiconductor memory device according to claim 10 , wherein the product code is a two-dimensional product code by a first code and a second code.

12 . The semiconductor memory device according to claim 11 , comprising:
a first parity generation circuit including the remainder calculating and retaining section that performs coding processing by the first code and generates a parity of the first code; and a second parity generation circuit that performs coding processing by the second code and generates a parity of the second code, wherein the common parity generation circuit is the second parity generation circuit, the coding processing by the second code is performed together with the coding processing by the first code, the parity of the second code is retained in the retaining circuit, decoding processing by the second code is performed together with decoding processing by the first code, and the decoder includes a syndrome generation circuit that divides the parity of the second code retained in the retaining circuit by a minimal polynomial of the generator polynomial.

13 . The semiconductor memory device according to claim 12 , wherein the encoder and the decoder further share the first parity generation circuit.

14 . The semiconductor memory device according to claim 12 , wherein
the remainder calculation circuit is a linear feedback register, and the retaining circuit is a flip-flop.

15 . The semiconductor memory device according to claim 12 , wherein the first code and the second code are BCH codes.

16 . The semiconductor memory device according to claim 12 , wherein the first code is a BCH code and the second code is a Reed Solomon code.

17 . The semiconductor memory device according to claim 12 , wherein the memory section is a NAND flash memory, a NOR flash memory, a magnetoresistive random access memory, or a resistive random access memory.

18 . The semiconductor memory device according to claim 17 , wherein a memory cell of the memory section is a multi-value memory.

19 . An operation method for a semiconductor memory device comprising:
generating, with a remainder calculation circuit by a generator polynomial of a first parity generation circuit of an encoder, a first parity from data of a target column of recorded data in a matrix form and generating a second parity from the data of the target column by retaining, in a retaining circuit, an output of a remainder calculation circuit by a generator polynomial of a second parity generation circuit of the encoder; recording, in a memory section, a two-dimensional product-coded data to which the first parity and the second parity are given; reading out the two-dimensional product-coded data from the memory section; generating, with the remainder calculation circuit by the generator polynomial of the first parity generation circuit shared by a decoder and the encoder, the first parity from data of the target column of the two-dimensional product-coded data and generating, with a syndrome generation circuit of the decoder, a first syndrome from the first parity, correcting an error, an error position of which is specified, generating, with the remainder calculation circuit by the generator polynomial of the second parity generation circuit shared by the decoder and the encoder, second parity from the data of the target column of the coded data, the error of which is corrected, retaining an output of the remainder calculation circuit in the retaining circuit, and iteratively performing error correction until processing of all target columns is completed; generating, after completion of data processing of all target columns, a second syndrome from the second parity of a target row retained in the retaining circuit and correcting an error, an error position of which is specified; and iteratively performing the error correction until the data processing of all target rows is completed.

Assignees

• Toshiba Kk

Inventors

• Fujiwara Daisuke

Classifications

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• H03M13/2909 Primary

  Product codes · CPC title

• G06F11/1068

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• H03M13/6502

  Reduction of hardware complexity or efficient processing · CPC title

• G11C2029/0411

  Online error correction · CPC title