Apparatuses and methods for encoding using error protection codes

Patent metadata

Field	Value
Publication number	US-9448884-B2
Application number	US-201414336873-A
Country	US
Kind code	B2
Filing date	Jul 21, 2014
Priority date	Mar 5, 2012
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

Subject matter disclosed herein relates to error protection of data stored in and/or read from a memory device. Coefficient data representing canonical coefficients can be pre-computed by an apparatus before the apparatus is provided with program data, for example. For example, coefficient data may be pre-computed external to the apparatus and stored before program data is provided to an apparatus.

First claim

The invention claimed is:

1. An electronically-implemented method of protecting program data, the method comprising:
retrieving predetermined coefficient data from an external device for computation of an error protection code, the predetermined coefficient data representing canonical coefficients that are determined independent of program data and are employed to compute parity data from program data;
combining the predetermined coefficient data and the program data to compute an error protection code comprising parity data, wherein the parity data comprises a sum of products, wherein the products comprise the predetermined coefficient data multiplied by the program data; and
storing the program data with the error protection code in memory.

2. The method of claim 1 , further comprising computing or retrieving the predetermined coefficient data responsive to a selection of the error protection code.

3. The method of claim 2 , wherein computing or retrieving responsive to the selection of the error protection code comprises computing responsive to the selection of the error protection code by a user.

4. The method of claim 1 , further comprising using the stored program data and the stored parity data to correct one or more errors in the stored program data.

5. The method of claim 1 , further comprising computing the parity data in parallel.

6. The method of claim 1 , further comprising using the predetermined coefficient data to compute respective parity data for different sets of program data stored in different memory arrays.

7. The method of claim 1 , wherein the predetermined coefficient data is stored in a look-up table.

8. The method of claim 1 , wherein the error protection code comprises a generalized block oriented algebraic error protection code.

9. The method of claim 8 , wherein the generalized block oriented algebraic error protection code comprises a Bose, Chaudhuri, Hocquenghem (BCH) code or a Reed-Solomon code.

10. The method of claim 1 , wherein the predetermined coefficient data are based, at least in part, on a generator polynomial.

11. An apparatus comprising:
circuitry configured to compute parity data based, at least in part, on program data and on predetermined coefficient data, wherein the parity data comprises a sum of products, wherein the products comprise the predetermined coefficient data multiplied by the program data, wherein the predetermined coefficient data represent canonical coefficients that are determined independent of the program data, are employed to compute the parity data from the program data, and are received from an external device; and
a memory array configured to store the parity data with the program data.

12. The apparatus of claim 11 , wherein the circuitry comprises circuitry configured to compute the parity data in parallel.

13. The apparatus of claim 11 , wherein the circuitry includes an encoder.

14. The apparatus of claim 11 , wherein the predetermined coefficient data is stored in a look-up table included in the circuitry.

15. The apparatus of claim 11 , wherein the predetermined coefficient data comprises coefficient data computed external to the apparatus.

16. The apparatus of claim 11 , wherein the circuitry comprises combinational logic circuitry.

17. The apparatus of claim 11 , wherein the error protection code comprises a selectable error protection code.

18. The apparatus of claim 17 , wherein the selectable error protection code comprises a Bose, Chaudhuri, Hocquenghem (BCH) code or a Reed-Solomon code.

19. An apparatus comprising:
parity computing circuit blocks configured to compute associated parity data for corresponding groups of program data, the circuit blocks configured to apply predetermined coefficients to one or more groups of program data, wherein the predetermined coefficients represent canonical coefficients that are determined independent of the program data, are employed to compute the parity data from the program data, and are received from an external device, wherein the parity data comprises a sum of products, wherein the products comprise the predetermined coefficient data multiplied by the program data; and
a memory array configured to store the parity data with the program data.

20. The apparatus of claim 19 , wherein the parity computing circuit blocks are configured to operate in parallel.

Assignees

• Micron Technology Inc

Inventors

• Van Aken Stephen P

Classifications

• H04L1/0057

  Block codes (H04L1/0061, H04L1/0064 take precedence) · CPC title

• H03M13/151

  using error location or error correction polynomials · CPC title

• H03M13/159 Primary

  Remainder calculation, e.g. for encoding and syndrome calculation · CPC title

• H03M13/1595

  Parallel or block-wise remainder calculation · CPC title

• H03M13/1515

  Reed-Solomon codes · CPC title