Solid-state imaging device

Patent metadata

Field	Value
Publication number	US-9466641-B2
Application number	US-201314098115-A
Country	US
Kind code	B2
Filing date	Dec 5, 2013
Priority date	Jun 22, 2011
Publication date	Oct 11, 2016
Grant date	Oct 11, 2016

Abstract

A solid-state imaging device including: a semiconductor substrate of a first conductivity type, having a fixed electric potential; a dark-current drain region of a second conductivity type, formed on a portion of the semiconductor substrate; a connection region of the first conductivity type, formed on another portion of the semiconductor substrate where the dark-current drain region is not formed; a well region of the first conductivity type, covering the dark-current drain region and the connection region; and a first region and a second region, formed within the well region and constituting a part of a read transistor that reads signal charge generated by photoelectric conversion. The well region is maintained at a fixed electric potential by being connected to the semiconductor substrate via the connection region.

First claim

The invention claimed is:

1. A solid-state imaging device comprising:
a photoelectric converter generating charge by photoelectric conversion, and
a semiconductor substrate having a first surface and a second surface opposite to the first surface, the second surface facing the photoelectric converter, the semiconductor substrate including:
a base region of a first conductivity type, on a side of the first surface, having a fixed electric potential;
a well region of the first conductivity type, on a side of the second surface;
a first region of a second conductivity type, between the base region and the well region;
a connection region of the first conductivity type, between the base region and the well region, electrically connecting the base region and the well region to maintain the well region at the fixed electric potential; and
a floating diffusion in the well region, electrically connected to the photoelectric converter, for accumulating the charge, wherein

the first region overlaps the floating diffusion in plan view.

2. The solid-state imaging device of claim 1 further comprising:
a second region within the well region, the second region in combination with the floating diffusion constituting a part of a reset transistor that resets an electric potential of the floating diffusion, the floating diffusion being one of a source and a drain of the reset transistor, the second region being the other one of the source and the drain of the reset transistor, wherein
the connection region overlaps at least a portion of the reset transistor in plan view.

3. The solid-state imaging device of claim 2 , wherein the connection region overlaps no portion of the first region in plan view.

4. The solid-state imaging device of claim 1 , wherein
the well region has a third surface and a fourth surface opposite to the third surface, the fourth surface facing the photoelectric converter and being the second surface of the semiconductor substrate,
the first region has a fifth surface and a sixth surface opposite to the fifth surface, the sixth surface being in direct contact with the third surface,
a distance between the fourth surface and the sixth surface falls within a range of 2.5 μm to 5 μm.

5. The solid-state imaging device of claim 1 , wherein
the well region has a third surface and a fourth surface opposite to the third surface, the fourth surface facing the photoelectric converter and being the second surface of the semiconductor substrate,
the first region has a fifth surface and a sixth surface opposite to the fifth surface, the sixth surface being in direct contact with the third surface,
a distance between the fourth surface and the sixth surface falls within a range of 0.3 μm to 1 μm.

6. The solid-state imaging device of claim 1 further comprising:
a second region and a third region located within the well region and constituting a part of an amplifying transistor that amplifies a signal according to the charge, the second region and the third region respectively being a source and a drain of the amplifying transistor, respectively, wherein
the connection region overlaps at least a portion of the amplifying transistor in plan view.

7. The solid-state imaging device of claim 6 , wherein the connection region overlaps no portion of the first region in plan view.

8. The solid-state imaging device of claim 1 further comprising:
a second region and a third region located within the well region and constituting a part of a select transistor that provides an instruction indicating whether or not to read an amplified signal, the second region and the third region respectively serving as a source and a drain of the select transistor, wherein
the connection region overlaps at least a portion of the select transistor in plan view.

9. The solid-state imaging device of claim 8 , wherein the connection region overlaps no portion of the first region in plan view.

10. The solid-state imaging device of claim 1 , wherein the photoelectric converter comprises:
a first electrode over the well region;
a second electrode over the first electrode; and
a photoelectric conversion film, between the first electrode and the second electrode.

11. The solid-state imaging device of claim 1 , wherein the connection region overlaps no portion of the floating diffusion in plan view.

12. The solid-state imaging device of claim 11 , wherein the connection region overlaps no portion of the first region in plan view.

Assignees

• Panasonic Corp
• Panasonic Ip Man Co Ltd

Inventors

• Miyagawa Ryohei

Classifications

• H10W10/031

  of isolation regions comprising PN junctions · CPC title

• H10W10/30

  Isolation regions comprising PN junctions · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10F39/802 Primary

  Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes · CPC title