Memory devices

Patent metadata

Field	Value
Publication number	US-9466361-B2
Application number	US-201414518810-A
Country	US
Kind code	B2
Filing date	Oct 20, 2014
Priority date	May 22, 2008
Publication date	Oct 11, 2016
Grant date	Oct 11, 2016

Abstract

Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage.

First claim

The invention claimed is:

1. A memory device comprising:
a wordline;
a bitline;
a memory element between the wordline and the bitline; and
a diode between the wordline and the bitline, the diode comprising at least one undoped layer, the at least one undoped layer being devoid of silicon.

2. The memory device of claim 1 wherein the at least one undoped layer comprises an undoped dielectric layer.

3. The memory device of claim 1 wherein the at least one undoped layer comprises at least two undoped dielectric layers.

4. The memory device of claim 1 wherein the at least one undoped layer comprises an electrode.

5. The memory device of claim 1 wherein the diode is between the wordline and the memory element.

6. The memory device of claim 1 wherein the diode is only at a cross-point of the bitline and the wordline.

7. The memory device of claim 1 wherein the at least one undoped layer comprises at least three undoped layers.

8. The memory device of claim 1 wherein the diode further comprises:
a pair of electrodes, the at least one undoped layer between the pair of electrodes; and
two insulative layers between the pair of electrodes and each insulative layer stacked against the at least one undoped layer.

9. The memory device of claim 1 wherein the diode further comprises:
a pair of electrodes, the at least one undoped layer between the pair of electrodes; and
two insulative layers between the pair of electrodes and each insulative layer stacked against the at least one undoped layer, at least one of the two insulative layers is undoped.

10. The memory device of claim 1 wherein the at least one undoped layer comprises one or more compositions of the following group: aluminum nitride, aluminum oxide, hafnium oxide, magnesium oxide, niobium oxide, tantalum oxide, titanium oxide, yittrium oxide, and zirconium oxide.

11. A memory device comprising:
a wordline;
a bitline;
a memory element between the wordline and the bitline; and
a diode between the wordline and the bitline, the diode comprising at least two staked, undoped, and discrete dielectric layers.

12. The memory device of claim 11 wherein the diode is between the bitline and the memory element.

13. The memory device of claim 11 wherein the diode is between the wordline and the memory element.

14. The memory device of claim 11 wherein the diode is only at a cross-point of the bitline and the wordline.

15. The memory device of claim 11 wherein the memory element is only at a cross-point of the bitline and the wordline.

16. The memory device of claim 11 further comprising an insulative layer between the at least two stacked, undoped, and discrete dielectric layers, wherein the insulative layer comprises a monolayer.

17. The memory device of claim 11 wherein the at least two staked, undoped, and discrete dielectric layers comprise at least three staked and differently composed dielectric layers.

18. The memory device of claim 17 wherein the at least three staked and differently composed dielectric layers comprise undoped material.

19. The memory device of claim 11 wherein the at least two staked, undoped, and discrete dielectric layers comprise one or more compositions selected from the group consisting of aluminum nitride, aluminum oxide, hafnium oxide, magnesium oxide, niobium oxide, silicon nitride, silicon oxide, tantalum oxide, titanium oxide, yittrium oxide and zirconium oxide.

20. The memory device of claim 11 wherein the at least two staked, undoped, and discrete dielectric layers comprise more than three staked and discrete dielectric layers.

21. The memory device of claim 11 wherein the at least two staked, undoped and discrete layers comprises three stacked and discrete layers, and further comprising at two insulative layers, each of the two insulative layers stacked against two of the three stacked and discrete layers.

22. A memory device comprising:
a wordline;
a bitline;
a memory element between the wordline and the bitline;
a diode between the wordline and the bitline, the diode comprising at least one undoped layer; and
wherein the at least one undoped layer comprises at least two undoped dielectric layers.

23. The memory device of claim 22 wherein the at least two undoped layers comprises at least three undoped layers.

24. A memory device comprising:
a wordline;
a bitline;
a memory element between the wordline and the bitline; and
a diode between the wordline and the bitline, the diode comprising at least one undoped layer; and
wherein the diode further comprises:
a pair of electrodes, the at least one undoped layer between the pair of electrodes; and
two insulative layers between the pair of electrodes and each insulative layer stacked against the at least one undoped layer.

25. The memory device of claim 24 wherein at least one of the two insulative layers is undoped.

Assignees

• Micron Technology Inc
• Micron Technology Inc

Inventors

• Mouli Chandra

Classifications

• G11C11/5678

  using amorphous/crystalline phase transition storage elements · CPC title

• G11C2216/08

  Nonvolatile memory wherein data storage is accomplished by storing relatively few electrons in the storage layer, i.e. single electron memory · CPC title

• G11C11/5685

  using storage elements comprising metal oxide memory material, e.g. perovskites · CPC title

• G11C11/34

  using semiconductor devices · CPC title

• G11C13/0002 Primary

  using resistive RAM [RRAM] elements · CPC title