Method and apparatus for dicing wafers having thick passivation polymer layer

US9460966B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9460966-B2
Application numberUS-201314103529-A
CountryUS
Kind codeB2
Filing dateDec 11, 2013
Priority dateOct 10, 2013
Publication dateOct 4, 2016
Grant dateOct 4, 2016

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a front surface having a plurality of integrated circuits thereon involves forming a mask layer above the front surface of the semiconductor wafer. The method also involves laser scribing the mask layer and the front surface of the semiconductor wafer to provide scribe lines in the mask layer and partially into the semiconductor wafer. The laser scribing involves use of a dual focus lens to provide a dual focus spot beam. The method also involves etching the semiconductor wafer through the scribe lines to singulate the integrated circuits.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of dicing a semiconductor wafer comprising a front surface having a plurality of integrated circuits thereon, the method comprising: forming a mask layer above the front surface of the semiconductor wafer; laser scribing the mask layer and the front surface of the semiconductor wafer to provide scribe lines in the mask layer and partially into the semiconductor wafer, the laser scribing involving use of a dual focus lens to provide a dual focus spot beam, wherein the front surface of the semiconductor wafer comprises a passivation layer disposed between partially exposed metal pillar/solder bump pairs, wherein the mask layer is formed on the passivation layer and the metal pillar/solder bump pairs, wherein a first focus spot of the dual focus spot beam is located in the mask layer, above the passivation layer, and wherein a second focus spot of the dual focus spot beam is located below the passivation layer; and etching the semiconductor wafer through the scribe lines to singulate the integrated circuits. 2. The method of claim 1 , wherein the passivation layer has a thickness approximately in the range of 35-50 microns. 3. The method of claim 1 , wherein the dual focus spot beam is a stationary beam. 4. The method of claim 1 , wherein the dual focus spot beam is a moveable beam. 5. The method of claim 1 , wherein the laser scribing is performed with a femto-second based laser. 6. The method of claim 1 , wherein etching the semiconductor wafer comprises using a high density plasma etching process. 7. A system for dicing a semiconductor wafer comprising a plurality of integrated circuits, the system comprising: a factory interface; a laser scribe apparatus coupled with the factory interface and comprising a dual focus lens, wherein the dual focus lens is moveable; and a plasma etch chamber coupled with the factory interface. 8. The system of claim 7 , wherein the plasma etch chamber is housed on a cluster tool coupled with the factory interface, the cluster tool further comprising: a deposition chamber configured to form a water-soluble mask layer. 9. The system of claim 8 , the cluster tool further comprising: a wet/dry station. 10. The system of claim 7 , wherein the laser scribe apparatus includes a femto-second-based laser. 11. The system of claim 7 , wherein the plasma etch chamber is configured to generate a high density plasma. 12. A method of dicing a monocrystalline silicon substrate comprising a front surface having a plurality of integrated circuits thereon, the method comprising: forming a mask layer above the front surface of the monocrystalline silicon substrate, wherein the front surface of the monocrystalline silicon substrate comprises a polyimide passivation layer disposed between partially exposed metal pillar/solder bump pairs, and wherein the mask layer is formed on the polyimide passivation layer and the metal pillar/solder bump pairs; laser scribing the mask layer, the polyimide passivation layer, and the front surface of the monocrystalline silicon substrate to provide scribe lines in the mask layer, in the polyimide passivation layer, and partially into the monocrystalline silicon substrate, the laser scribing involving use of a dual focus lens to provide a dual focus spot beam, wherein the laser scribing is performed with a femto-second based laser, and wherein a first focus spot of the dual focus spot beam is located in the mask layer, above the polyimide passivation layer, and wherein a second focus spot of the dual focus spot beam is located below the polyimide passivation layer; and plasma etching the monocrystalline silicon substrate through the scribe lines to singulate the integrated circuits. 13. The method of claim 12 , wherein the polyimide passivation layer has a thickness approximately in the range of 35-50 microns. 14. The method of claim 12 , wherein the dual focus spot beam is a stationary beam. 15. The method of claim 12 , wherein the dual focus spot beam is a moveable beam.

Assignees

Inventors

Classifications

  • comprising a chamber adapted to a particular process · CPC title

  • characterised by their behaviour during the process, e.g. soluble masks or redeposited masks · CPC title

  • characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane · CPC title

  • of Group IV materials · CPC title

  • H10P54/00Primary

    Cutting or separating of wafers, substrates or parts of devices · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9460966B2 cover?
Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a front surface having a plurality of integrated circuits thereon involves forming a mask layer above the front surface of the semiconductor wafer. The method also involves laser scribing the mask layer an…
Who is the assignee on this patent?
Lei Wei-Sheng, Eaton Brad, Kumar Ajay, and 1 more
What technology area does this patent fall under?
Primary CPC classification H10P54/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 04 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).