Hybrid substrates, semiconductor packages including the same and methods for fabricating semiconductor packages

Patent metadata

Field	Value
Publication number	US-9460937-B2
Application number	US-201414451982-A
Country	US
Kind code	B2
Filing date	Aug 5, 2014
Priority date	Dec 15, 2010
Publication date	Oct 4, 2016
Grant date	Oct 4, 2016

Abstract

Provided are a hybrid substrate, a semiconductor package including the same, and a method for fabricating the semiconductor package. The hybrid substrate may include an insulation layer, and an organic layer. The insulation layer may include a top, a bottom opposite to the top, and a conductive pattern having different pitches. The organic layer may be connected to the bottom of the insulation layer, and may include a circuit pattern connected to the conductive pattern. The conductive pattern may include a first metal pattern, and a second conductive pattern. The first metal pattern may have a first pitch, and may be disposed in the top of the insulation layer. The second conductive pattern may have a second pitch greater than the first pitch, and may be extended from the first metal pattern to be connected to the circuit pattern through the insulation layer.

First claim

What is claimed is:

1. A method for fabricating a semiconductor package, the method comprising:
providing a substrate including a first layer and a second layer, the providing a substrate including,
forming the first layer including a conductive pattern with a first pitch and a second pitch greater than the first pitch, the forming the first layer including,
forming an inorganic insulation layer having a first surface and a second surface, the second surface being opposite to the first surface and facing the second layer, and
forming the conductive pattern including,
forming a first metal pattern with the first pitch on the first surface of the inorganic insulation layer,
forming a second metal pattern with the second pitch on the second surface of the inorganic insulation layer, and
forming an internal metal pattern in the inorganic insulation layer to connect the first metal pattern to the second metal pattern, and

forming the second layer on the first layer, the second layer having a circuit pattern with the second pitch, the circuit pattern connected to the conductive pattern;

providing a semiconductor chip on the substrate, the semiconductor chip including a plurality of chip pads having the first pitch;
connecting the chip pads to the conductive pattern to electrically connect the semiconductor chip to the substrate;
forming a molding layer on the semiconductor chip; and
forming an external terminal connected to the circuit pattern.

2. The method of claim 1 , further comprising:
providing a support plate;
sequentially forming the first and second layers on the support plate; and
removing the support plate after forming the first and second layers.

3. The method of claim 1 , wherein the forming the second layer includes,
forming an organic insulation layer on the second surface of the inorganic insulation layer, and
forming the circuit pattern in the organic insulation layer such that the circuit pattern is connected to the second metal pattern.

4. The method of claim 3 , wherein the providing a substrate further includes forming a third layer on the organic insulation layer, and the third layer includes a second organic insulation layer having a second circuit pattern with a third pitch greater than the second pitch.

5. A method for fabricating a semiconductor package, the method comprising:
providing a substrate including a first layer and a second layer, the providing a substrate including,
forming a flexible film including a conductive pattern to provide the first layer, the conductive pattern having a first pitch and a second pitch greater than the first pitch, the forming a flexible film including,
providing a polymer film having a first surface and a second surface, the second surface being opposite to the first surface and facing the second layer, and
forming the conductive pattern, the forming the conductive pattern including,
forming a metal pattern with the first pitch on the first surface of the polymer film,
forming a plurality of first vias penetrating through the metal pattern and the polymer film and having the first pitch, while being connected to the metal pattern,
forming a plurality of second vias penetrating through the polymer film and having the second pitch, and
forming an interconnection pattern between the first vias and the second vias to provide electrical connection therebetween;

forming an organic substrate on the flexible film to provide the second layer, the organic substrate including a circuit pattern having the second pitch and connected to the conductive pattern;

providing a semiconductor chip on the substrate, the semiconductor chip including a plurality of chip pads having the first pitch;
connecting the chip pads to the conductive pattern to electrically connect the semiconductor chip to the substrate;
forming a molding layer on the semiconductor chip;
forming an external terminal connected to the circuit pattern; and
connecting the flexible film to the organic substrate through an adhesive layer.

6. The method of claim 1 , wherein the forming the conductive pattern forms the second metal pattern to not have the first pitch on the second surface of the inorganic insulation layer.

7. The method of claim 1 , wherein the first metal pattern is connected to the second metal pattern via the internal metal pattern penetrating through the inorganic insulation layer.

8. The method of claim 7 , wherein the internal metal pattern is directly connected to the second metal pattern without being redistributed on the second surface of the inorganic insulation layer.

9. The method of claim 1 , wherein the forming a second metal pattern forms the second metal pattern to not have a pitch smaller than the second pitch.

10. The method of claim 5 , wherein the second vias are directly connected to the circuit pattern without being redistributed.

Assignees

• Son Daewoo
• Kim Chulwoo
• Samsung Electronics Co Ltd

Inventors

• Son Daewoo
• Kim Chulwoo

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

• H10W90/271

  the chips having passive surfaces facing each other, i.e. in a back-to-back arrangement · CPC title