Voltage sampling scheme with dynamically adjustable sample rates

Patent metadata

Field	Value
Publication number	US-9350326-B2
Application number	US-201414455195-A
Country	US
Kind code	B2
Filing date	Aug 8, 2014
Priority date	Aug 8, 2014
Publication date	May 24, 2016
Grant date	May 24, 2016

Abstract

A apparatus including a clock source and a comparison circuit is presented. The clock source may be configured to generate a clock signal. The comparison circuit may be configured select a first frequency of the clock signal and to receive a plurality of voltage signal inputs for comparison. The comparison circuit may be further configured to compare a voltage level of a first voltage signal input of the plurality of voltage signal inputs to a voltage level of a second voltage signal input of the plurality of voltage signal inputs responsive to an active edge of the clock signal. The comparison circuit may also be configured to determine a comparison value corresponding to the comparison of the voltage levels and to select a second frequency of the clock signal dependent upon the comparison value, in which the second frequency is different than the first frequency.

First claim

What is claimed is:

1. An apparatus, comprising:
a clock source configured to generate a clock signal;
a comparison circuit coupled to the clock source, wherein the comparison circuit is configured to:
select a first frequency of the clock signal;
receive a plurality of voltage signal inputs for comparison;
compare a voltage level of a first voltage signal input of the plurality of voltage signal inputs to a voltage level of a second voltage signal input of the plurality of voltage signal inputs in response to an active edge of the clock signal;
determine a comparison value corresponding to the comparison of the voltage levels; and
select a second frequency of the clock signal dependent upon the comparison value, wherein the second frequency is different than the first frequency;

wherein the plurality of voltage signal inputs include a first reference voltage signal and an output signal of a voltage regulator, and wherein the comparison circuit is further configured to:
enable the first reference voltage signal in response to the active edge of the clock signal; and
compare the first reference voltage signal to the output signal of the voltage regulator in response to a determination that a predetermined amount of time has elapsed since the first reference voltage signal was enabled.

2. The apparatus of claim 1 wherein the clock source comprises a multiplex circuit, wherein the clock signal corresponds to an output of the multiplex circuit, and wherein to select the second frequency, the comparison circuit is further configured to select a different input to the multiplex circuit as the clock signal.

3. The apparatus of claim 1 wherein the comparison circuit is further configured to disable the first reference voltage signal in response to the determination of the comparison value corresponding to the comparison of the voltage levels.

4. The apparatus of claim 1 wherein the plurality of voltage signal inputs includes a second reference voltage signal, wherein a voltage level of the second reference voltage signal is lower than a voltage level of the first reference voltage signal.

5. The apparatus of claim 4 wherein the comparison circuit is further configured to determine the comparison value dependent upon a determination that a voltage level of the output signal of the voltage regulator is greater than or equal to the voltage level of the first reference voltage signal, is between the voltage level of the first reference voltage signal and the voltage level of the second reference voltage signal, or is less than or equal to the voltage level of the second reference voltage signal.

6. The apparatus of claim 1 , wherein the comparison circuit is further configured to:
store the comparison value, and
select the second frequency of the clock signal dependent upon a most recent comparison value and one or more previously stored comparison values.

7. The apparatus of claim 1 , wherein the comparison circuit is further configured to select the second frequency of the clock signal to be higher than the first frequency of the clock signal in response to a determination that a voltage level of the first reference voltage signal is higher than a voltage level of the output signal of the voltage regulator.

8. A method, comprising:
selecting a first frequency of a clock signal;
receiving a plurality of signals for comparison, wherein the plurality of signals include a first reference voltage signal and an output signal of a voltage regulator;
enabling the first reference voltage signal in response to the active edge of the clock signal;
comparing a voltage level of a first signal of the plurality of signals to a voltage level of a second signal of the plurality of signals in response to an active edge of the clock signal, wherein comparing the voltage level of the first signal to a voltage level of the second signal comprises comparing the first reference voltage signal to the output signal of the voltage regulator in response to determining that a predetermined amount of time has elapsed since the active edge of the clock signal;
determining a comparison value dependent upon the comparison of the voltage levels; and
selecting a second frequency of the clock signal dependent upon the comparison value wherein the second frequency is different than the first frequency.

9. The method of claim 8 wherein selecting a second frequency of the clock signal dependent upon the comparison value comprises adjusting a multiplex circuit to output the clock signal at the second frequency.

10. The method of claim 8 further comprising disabling the first reference voltage signal in response to determining the comparison value dependent upon the comparison of the voltage levels.

11. The method of claim 8 wherein the plurality of signals includes a second reference voltage signal, wherein a voltage level of the second reference voltage signal is lower than a voltage level of the first reference voltage signal.

12. The method of claim 11 further comprising determining the comparison value dependent upon a determination that a voltage level of the output signal of the voltage regulator is greater than or equal to the voltage level of the first reference voltage signal, is between the voltage level of the first reference voltage signal and the voltage level of the second reference voltage signal, or is less than or equal to the voltage level of the second reference voltage signal.

13. The method of claim 8 , further comprising:
storing the comparison value, and
selecting the second frequency of the clock signal dependent upon a most recent comparison value and one or more previously stored comparison values.

14. The method of claim 8 , further comprising selecting the second frequency of the clock signal to be higher than the first frequency of the clock signal in response to determining that a voltage level of the first reference voltage signal is higher than a voltage level of the output signal of the voltage regulator.

15. A system, comprising:
a reference voltage circuit configured to generate at least a first reference voltage signal;
a voltage generation circuit configured to generate an output voltage signal;
a voltage comparator module, coupled to the reference voltage circuit and the voltage generation circuit, wherein the voltage comparator module is configured to:
select a first frequency of a clock signal;
enable the first reference voltage signal in response to the active edge of the clock signal;
receive the first reference voltage signal and the output voltage signal for comparison;
compare a voltage level of the first reference voltage signal to a voltage level of the output voltage signal in response to an active edge of the clock signal;
determine a comparison value dependent upon the comparison of the voltage levels; and
select a second frequency of the clock signal dependent upon the comparison value;

wherein to compare the first reference voltage signal to the output voltage signal, the voltage comparator module is further configured to compare the first reference voltage signal to the output voltage signal in response to a determination that a predetermined amount of time has elapsed since the first reference voltage signal was enabled.

16. The system of claim 15 wherein the voltage comparator module includes a multiplex circuit and wherein to select the second frequency of the clock signal dependent upon the comparison value, the voltage comparator module is further configured to adjust the multiplex circuit to output the clock signal at the second frequency.

Assignees

• Apple Inc

Inventors

• Tang Bo
• Bhatia Ajay Kumar

Classifications

• H03K3/012 Primary

  Modifications of generator to improve response time or to decrease power consumption · CPC title

• H03K5/249

  using clock signals · CPC title

• H03K5/24 Primary

  the characteristic being amplitude · CPC title

• H03K19/0013

  in field effect transistor circuits · CPC title