Storage module and method for using healing effects of a quarantine process

Patent metadata

Field	Value
Publication number	US-9455038-B2
Application number	US-201414510945-A
Country	US
Kind code	B2
Filing date	Oct 9, 2014
Priority date	Aug 20, 2014
Publication date	Sep 27, 2016
Grant date	Sep 27, 2016

Abstract

A storage module and method are provided for using healing effects of a quarantine process. In one embodiment, a storage module is provided comprising a controller and a memory. The controller is configured to identify a set of memory cells in the memory that contains a bit error rate above a threshold, wherein the bit error rate is above the threshold due to trapped charge in dielectrics of the memory cells. The controller is also configured to quarantine the set of memory cells for a period of time, wherein while the set of memory cells is quarantined, heat generated by the storage module anneals the set of memory cells to at least partially remove the trapped charge.

First claim

What is claimed is:

1. A storage module comprising:
a memory; and
a controller in communication with the memory, wherein the controller is configured to:
identify a word line having a set of memory cells in the memory that contains a bit error rate above a threshold, wherein the bit error rate is above the threshold due to trapped charge in dielectrics of the memory cells;
program the word line; and
after the word line has been programmed, quarantine the word line for a period of time, wherein while the word line is quarantined, heat generated by the storage module anneals the set of memory cells to at least partially remove the trapped charge;

wherein the word line is one of a plurality of word lines in a block of memory, and wherein the controller is further configured to continue to use the other word lines in the block to store data while the word line is quarantined and to program dummy data in one or more word lines surrounding the quarantined word line.

2. The storage module of claim 1 , wherein the word line is one of a plurality of word lines in a block of memory, and wherein the controller is further configured to slow a circulation of the block to allow enough time for heat generated by the storage module to anneal the set of memory cells to at least partially remove the trapped charge.

3. The storage module of claim 1 , wherein the controller is further configured to test the set of memory cells to see if there is an improvement in the bit error rate.

4. The storage module of claim 3 , wherein the controller is further configured to end the quarantine of the set of memory cells in response to determining that the bit error rate is below the threshold.

5. The storage module of claim 3 , wherein the controller is further configured to continue the quarantine of the set of memory cells in response to determining that there is an improvement in the bit error rate but that the bit error rate is still not below the threshold.

6. The storage module of claim 3 , wherein the controller is further configured to permanently quarantine the set of memory cells in response to determining that there is no improvement in the bit error rate.

7. The storage module of claim 1 , wherein the set of memory cells is programmed with user data.

8. The storage module of claim 1 , wherein the memory cells store multiple bits per cell, and wherein the set of memory cells are programmed such that all of the bits of the memory cell are in a programmed state.

9. The storage module of claim 1 , wherein the period of time is dependent on a temperature in the storage module.

10. The storage module of claim 9 , wherein the temperature is determined by a temperature sensor in the storage module, and wherein the period of time is measured by clock signal in the controller.

11. The storage module of claim 9 , wherein the temperature and period of time are measured by a sentinel cell's voltage drift.

12. The storage module of claim 1 , wherein the heat is generated by the storage module in its normal operation.

13. The storage module of claim 1 , wherein the memory is a three-dimensional memory.

14. The storage module of claim 1 , wherein the storage module is embedded in a host.

15. The storage module of claim 1 , wherein the storage module is removably connected to a host.

16. The storage module of claim 1 , wherein the storage module is a solid-state drive.

17. A method for using healing effects of a quarantine process, the method comprising:
performing the following in a storage module:
identifying a word line having a set of memory cells in the memory that contains a bit error rate above a threshold, wherein the bit error rate is above the threshold due to trapped charge in dielectrics of the memory cells;
programming the word line; and
after the word line has been programmed, quarantining the word line for a period of time, wherein while the word line is quarantined, heat generated by the storage module anneals the set of memory cells to at least partially remove the trapped charge;

wherein the word line is one of a plurality of word lines in a block of memory, and wherein the method further comprises continuing to use the other word lines in the block to store data while the word line is quarantined and programming dummy data in one or more word lines surrounding the quarantined word line.

18. The method of claim 17 , wherein the word line is one of a plurality of word lines in a block of memory, and wherein the method further comprises continuing to use the other word lines in the block to store data while the word line is quarantined.

19. The method of claim 18 further comprising programming dummy data in one or more word lines surrounding the quarantined word line.

20. The method of claim 17 , wherein the word line is one of a plurality of word lines in a block of memory, and wherein the method further comprises slowing a circulation of the block to allow enough time for heat generated by the storage module to anneal the set of memory cells to at least partially remove the trapped charge.

21. The method of claim 17 further comprising testing the set of memory cells to see if there is an improvement in the bit error rate.

22. The method of claim 21 further comprising ending the quarantine of the set of memory cells in response to determining that the bit error rate is below the threshold.

23. The method of claim 21 further comprising continuing the quarantine of the set of memory cells in response to determining that there is an improvement in the bit error rate but that the bit error rate is still not below the threshold.

24. The method of claim 21 further comprising permanently quarantining the set of memory cells in response to determining that there is no improvement in the bit error rate.

25. The method of claim 17 , wherein the memory cells store multiple bits per cell, and wherein the set of memory cells are programmed such that all of the bits of the memory cell are in a programmed state.

26. The method of claim 17 , wherein the period of time is dependent on a temperature in the storage module.

27. The method of claim 26 , wherein the temperature is determined by a temperature sensor in the storage module, and wherein the period of time is measured by clock signal in the storage module.

28. The method of claim 26 , wherein the temperature and period of time are measured by a sentinel cell's voltage drift.

29. The method of claim 17 , wherein the heat is generated by the storage module in its normal operation.

30. The method of claim 17 , wherein the memory is a three-dimensional memory.

31. The method of claim 17 , wherein the storage module is embedded in a host.

32. The method of claim 17 , wherein the storage module is removably connected to a host.

33. The method of claim 17 , wherein the storage module is a solid-state drive.

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Tuers Daniel E
• Lee Dana
• Chin Henry
• Manohar Abhijeet

Classifications

• G11C16/3418

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C11/5671 Primary

  using charge trapping in an insulator · CPC title

• G11C16/349

  Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles · CPC title

• G11C29/4401

  for self repair · CPC title

• G11C16/3404 Primary

  Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells · CPC title