Nonvolatile memory devices and driving methods thereof

Patent metadata

Field	Value
Publication number	US-2015138890-A1
Application number	US-201514610584-A
Country	US
Kind code	A1
Filing date	Jan 30, 2015
Priority date	Feb 9, 2011
Publication date	May 21, 2015
Grant date	—

Abstract

Nonvolatile memory devices including memory cell arrays with a plurality of cell strings connected between a substrate and a plurality of bit lines and selected by selection lines, and a gating circuit configured to drive the selection lines in at least two directions.

First claim

1 . A nonvolatile memory device, comprising:
a memory cell array including a plurality of cell strings formed in a direction perpendicular to a substrate layer, each of the plurality of cell strings is connected between the substrate layer and a corresponding bit line, wherein each of the plurality of cell strings comprises:
at least one string selection transistor connected to a string selection line;
a plurality of cell transistors, each of cell transistors is connected in common with a word line of a corresponding layer; and
at least one ground selection transistor connected to a ground selection line for connecting the plurality of cell transistors to the substrate layer;
a decoder configured to drive at least one of the string selection line and the ground selection line in at least two directions.

2 . The nonvolatile memory device of claim 1 , wherein the decoder comprises:
a first gating circuit configured to provide at least one of a string selection signal to the string selection line, a ground selection signal to the ground selection line, and word line voltages to the plurality of word lines associated with the plurality of cell transistors on a first side of the memory cell array, and a second gating circuit configured to provide at least one of the string selection signal to the string selection line, the ground selection signal to the ground selection line on a second side of the memory cell array.

3 . The nonvolatile memory device of claim 2 , wherein the first gating circuit and the second gating circuit are configured to provide the string selection signal to the string selection line on the first side and the second side of the memory cell array concurrently.

4 . The nonvolatile memory device of claim 2 , wherein the first gating circuit and the second gating circuit are configured to provide the ground selection signal to the ground selection line on the first side and the second side of the memory cell array concurrently.

5 . The nonvolatile memory device of claim 2 , wherein the first gating circuit and the second gating circuit are configured to provide the word line voltages to the plurality of word lines on one of the first side and the second side of the memory cell array.

6 . The nonvolatile memory device of claim 2 , wherein the first gating circuit comprises:
first pass transistors configured to provide a plurality of string selection signals to a plurality of string selection lines on the first side of the at least one of selection lines in response to a block selection signal; second pass transistors configured to provide the plurality of word line voltages to the plurality of word lines in response to the block selection signal; and a third pass transistor configured to provide the ground selection signal to a ground selection line on the first side in response to the block selection signal.

7 . The nonvolatile memory device of claim 6 , wherein the second gating circuit comprises:
fourth pass transistors configured to provide the plurality of string selection signals to the plurality of string selection lines on the second side in response to the block selection signal; and a fifth pass transistor configured to provide the ground selection signal to the ground selection line on the second side in response to the block selection signal.

8 . The nonvolatile memory device of claim 7 , wherein the first to fifth pass transistors are high voltage transistors.

9 . The nonvolatile memory device of claim 2 , wherein the first and second gating circuits include ground transistors configured to ground the at least one of string selection line and ground selection line in response to a block shut-off signal.

10 . The nonvolatile memory device of claim 1 , wherein each of the cell transistors include a charge trap layer.

11 . A method of reading a nonvolatile memory device, the nonvolatile memory device including a plurality of cell strings formed in a direction perpendicular to a substrate layer, each of the plurality of cell strings including at least one selection transistor and cell transistor, the method comprising:
pre-charging a bit line connected to a selected cell string of the plurality of cell strings; applying a word line voltage to a word line of the cell transistor, and at least one selection signal to at least one selection line connected to the at least one selection transistor on both side of the at least one selection line to setup the at least one selection signal more rapidly than word line voltage.

12 . The method of claim 9 , wherein the at least one selection transistor comprises a string selection transistor connected to a string selection line and a ground selection transistor connected to a ground selection line.

13 . The method of claim 9 , wherein the at least one selection transistor corresponds to a string selection transistor connected to a string selection line.

14 . The method of claim 9 , wherein the at least one selection transistor corresponds to a ground selection transistor connected to a ground selection line.

15 . The method of claim 9 , wherein the cell transistor includes a charge trap layer.

16 . The method of claim 9 , wherein the at least one selection line is driven by at least two driving circuit, and the word line is driven by single driving circuit.

17 . A storage device, comprising:
a nonvolatile memory device including a plurality of cell strings formed in a direction perpendicular to a substrate layer, wherein each of the plurality of cell strings are driven via at least one string selection line, a plurality of word lines, and at least one ground selection line; and a memory controller configured to control the nonvolatile memory device to select at least one of the plurality of cell strings at a read operation, wherein the at least one string selection line or the at least one ground selection line is driven in at least two directions.

18 . The storage device of claim 17 , wherein the nonvolatile memory device comprises:
a first gating circuit configured to drive the at least one string selection line and the at least one ground selection line; and a second gating circuit configured to drive the at least one string selection line.

19 . The storage device of claim 18 , wherein the first gating circuit further drives the plurality of word lines in single direction.

20 . The storage device of claim 17 , wherein the plurality of cell strings comprises a non-volatile memory that is monolithically formed in one or more physical levels of memory cells having active areas disposed above a silicon substrate.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Kyung-Hwa
• Nam Sang-Wan
• Chae Donghyuk
• Yoon Chiweon

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• H01L27/11582

  Electricity · mapped topic

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/0466

  comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence) · CPC title