Electronic counter in non-volatile limited endurance memory

Patent metadata

Field	Value
Publication number	US-9454471-B2
Application number	US-201314029659-A
Country	US
Kind code	B2
Filing date	Sep 17, 2013
Priority date	Sep 27, 2012
Publication date	Sep 27, 2016
Grant date	Sep 27, 2016

Abstract

An electronic counter is provided having a sequence of memory cells and increment logic. Each memory cell of the sequence is non-volatile and supports a one state and a zero state. The one state can also be referred to as a ‘programmed state’, the zero state as an ‘erased state’. The counter is configured to represent at least part of a current counting-state of the counter as a pattern of one and zero states in the memory cells of the sequence of memory cells, and increment logic configured to advance the pattern of one and zero states to a next pattern to represent an increment of the counter.

First claim

The invention claimed is:

1. An electronic counter comprising
multiple sequences of memory cells, each memory cell of the multiple sequences being non-volatile and supporting a one state and a zero state, the counter being configured to represent multiple sub-states of a current counting state of the counter as a pattern of one and zero states in the memory cells of the multiple sequences of memory cells,
wherein all-but one of the multiple sequences are configured with a pattern indicating that the sequence is inactive, one of the multiple sequences is configured with a different pattern than the pattern indicating that the sequence is inactive, the pattern being all one states or all zero states, the counter comprising
increment logic configured to
determine an active sequence of the multiple sequences not storing the inactive pattern, and configured to advance the active sequence to a next pattern, upon the next pattern reaching the inactive pattern, the increment logic further advances a next sequence of the multiple sequences, wherein the
increment logic is configured to advance the pattern of one and zero states to a next pattern to represent an increment of the counter, the increment logic comprising programming increment logic and erasing increment logic, the increment logic being configured to alternate between a programming phase in which the programming increment logic advances the pattern, and an erasing phase in which the erasing increment logic advances the pattern, wherein
the programming increment logic is configured to program a cell of the sequence of non-volatile memory cells from a zero state to a one state, the program phase terminating when all memory cells of the sequence of memory cells are in the one state,
the erasing increment logic is configured to erase a cell of the sequence of non-volatile memory cells from a one state to a zero state, the erase phase terminating when all memory cells of the sequence of memory cells are in the zero state;
a non-volatile high-word memory, the counter being configured to represent a further part of the counting-state of the counter in the high-word memory,
a high-word increment logic for advancing the part of the counting-state represented in the high-word memory, the counter being configured for the high-word increment logic to perform the incrementing upon overflow of the sequence of memory cell, determined by
the program phase terminating, or
the erasing phase terminating;

a further non-volatile high-word memory, wherein the high-word increment logic is configured to
determine which memory of the high-word memory and the further high-word memory stores the higher number, and which stores the lower number,
incrementing the higher number, and
writing the incremented higher number to the memory that stores the lower number.

2. A counter as in claim 1 , wherein
the non-volatile high-word memory represents a base-2 positional number, and wherein the high-word increment logic is configured to increment the further memory according to a base-2 positional number system, or
the non-volatile high-word memory represents a bit-pattern in Gray encoding, and wherein the high-word increment logic is configured to advance the bit-pattern to the next bit-pattern according to the Gray encoding.

3. A counter as in claim 1 , wherein the increment logic is configured to determine a current phase from the state of a final memory cell in the sequence of memory cells, wherein
the current phase is the programming phase if the final memory cell is in a zero state, and
the current phase is the erasing phase if the final memory cell is in a one state.

4. A counter as in claim 1 , wherein the increment logic is configured to perform a binary search to find the next cell.

5. A counter as in claim 1 , comprising a volatile index memory, for storing an index pointing to a memory cell in the sequence of memory cells representing the next cell, the increment logic being configured to increment the index memory upon performing an increment.

6. A counter as in claim 1 , wherein the memory cells are memory cells in a larger non-volatile memory, the larger memory being organized in multiple memory words, wherein multiple final memory cells of the multiple sequences of memory cells lie in the same memory words.

7. A counter in claim 6 , wherein the number of bits in a memory word equals the number of sequences in the multiple sequences.

8. A counter as in claim 1 wherein the memory cells in the sequence of memory cells are EEPROM memory cells, and optionally wherein the high-word memory is EEPROM memory, and optionally wherein all memory cells of multiple sequences of memory cells are EEPROM memory cells.

9. An electronic device comprising the counter as claimed in claim 1 .

10. A counter as in claim 1 , wherein
the programming increment logic is configured to determine the first cell of the sequence of non-volatile memory cells having a zero value, and program the first cell from a zero state to a one state,
the erasing increment logic is configured to determine the first cell of the sequence of non-volatile memory cells having a one value, and program the first cell from a one state to a zero state.

11. A counter as in claim 1 , comprising a volatile index memory, for storing an index pointing to a memory cell in the sequence of memory cells representing the next cell, the increment logic being configured to increment the index memory upon performing an increment.

12. An electronic counter comprising:
multiple sequences of memory cells, each memory cell of the multiple sequences being non-volatile and supporting a one state and a zero state, the counter being configured to represent multiple sub-states of a current counting state of the counter as a pattern of one and zero states in the memory cells of the multiple sequences of memory cells,
wherein all-but one of the multiple sequences are configured with a pattern indicating that the sequence is inactive, one of the multiple sequences is configured with a different pattern than the pattern indicating that the sequence is inactive, the pattern being all one states or all zero states, the counter comprising
increment logic configured to
determine an active sequence of the multiple sequences not storing the inactive pattern, and configured to advance the active sequence to a next pattern, upon the next pattern reaching the inactive pattern, the increment logic further advances a next sequence of the multiple sequences, wherein the increment logic is configured to advance the pattern of one and zero states to a next pattern to represent an increment of the counter, the increment logic comprising programming increment logic and erasing increment logic, the increment logic being configured to alternate between a programming phase in which the programming increment logic advances the pattern, and an erasing phase in which the erasing increment logic advances the pattern, wherein
the programming increment logic is configured to program a cell of the sequence of non-volatile memory cells from a zero state to a one state, the program phase terminating when all memory cells of the sequence of memory cells are in the one state,
the erasing increment logic is configured to erase a cell of the sequence of non-volatile memory cells from a one state to a zero state, the erase phase terminating when all memory cells of the sequence of memory cells are in the zero state;
wherein the memory cells are memory cells in a larger non-volatile memory, the larger memory being organized in multiple memory words, wherein multiple final memory cells of the multiple sequences of memory cells lie in

Assignees

• Nxp Bv

Inventors

• Feldhofer Martin
• Amtmann Franz
• Ostertun Soenke
• Da Conceicao Alicia

Classifications

• H03K21/403 Primary

  Arrangements for storing the counting state in case of power supply interruption · CPC title

• G06F12/00 Primary

  Accessing, addressing or allocating within memory systems or architectures (digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06) · CPC title