Non-volatile counter system, counter circuit and power management circuit with isolated dynamic boosted supply

Patent metadata

Field	Value
Publication number	US-11200030-B2
Application number	US-201916711042-A
Country	US
Kind code	B2
Filing date	Dec 11, 2019
Priority date	Jul 27, 2017
Publication date	Dec 14, 2021
Grant date	Dec 14, 2021

Abstract

Disclosed examples include non-volatile counter systems to generate and store a counter value according to a sensor pulse signal, and power circuits to generate first and second supply voltage signals to power first and second power domain circuits using power from the sensor pulse signal, including a switch connected between first and second power domain supply nodes, a boost circuit, and a control circuit to selectively cause the switch to disconnect the first and second power domain circuits from one another after the first supply voltage signal rises above a threshold voltage in a given pulse of the sensor pulse signal, and to cause the boost circuit to boost the second supply voltage signal after the regulator output is disconnected from the second power domain supply node in the given pulse.

First claim

The following is claimed:

1. An integrated circuit, comprising:
a first power domain circuit comprising a logic circuit, the first power domain circuit having a first power domain supply node;
a second power domain circuit comprising a non-volatile memory circuit, the second power domain circuit having a second power domain supply node;
a supply circuit having a sensor pulse input and a supply output;
a power management circuit coupled to the first power domain circuit, to the second power domain circuit and to the supply circuit, the power management circuit comprising:
a regulator circuit, having an input coupled to the supply output and a regulator output coupled to the first power domain supply node;
a switch coupled between the first power domain supply node and the second power domain supply node, the switch having a control node;
a boost circuit having a boost output coupled to the second power domain supply node; and
a control circuit having a control output coupled to the control node of the switch.

2. The integrated circuit of claim 1 ,
wherein the logic circuit includes a first interface to send and receive first data signals representing a counter value, the logic circuit configured to selectively update the counter value according to the sensor pulse input; and
wherein the non-volatile memory circuit includes a second interface to send and receive second data signals representing the counter value, and wherein the non-volatile memory circuit is configured to store the counter value.

3. The integrated circuit of claim 1 , wherein the supply circuit is a rectifier.

4. The integrated circuit of claim 1 , wherein the regulator circuit is configured to regulate a first supply voltage at the first power domain supply node according to a reference voltage.

5. The integrated circuit of claim 4 , wherein the regulator circuit is configured to regulate the first supply voltage to a value less than a second supply voltage signal at the second power domain supply node.

6. The integrated circuit of claim 4 , wherein the regulator circuit is configured to regulate the first supply voltage to a value less than a minimum required operating voltage of the non-volatile memory circuit.

7. The integrated circuit of claim 6 , wherein the regulator circuit is a low dropout regulator.

8. The integrated circuit of claim 6 , wherein the boost circuit includes:
a buffer circuit, including a buffer input connected to the control output to receive a control signal from the control output, and a buffer output; and
a capacitor, including a first terminal connected to the second power domain supply node, and a second terminal connected to the buffer output;
wherein the control circuit is configured to provide the control signal including a rising edge a predetermined time after a first supply voltage signal at the first power domain supply node rises above a threshold voltage to raise a voltage at the second terminal of the capacitor to provide a second supply voltage signal at the second power domain supply node.

9. The integrated circuit of claim 1 , wherein the regulator circuit is a low dropout regulator.

10. The integrated circuit of claim 1 , wherein the regulator circuit is configured to regulate a first supply voltage at the first power domain supply node to a value less than a second supply voltage signal at the second power domain supply node.

11. The integrated circuit of claim 1 , wherein the regulator circuit is configured to regulate a first supply voltage at the first power domain supply node to a value less than a minimum required operating voltage of the non-volatile memory circuit.

12. The integrated circuit of claim 1 , wherein the boost circuit includes:
a buffer circuit, including a buffer input connected to the control output to receive a control signal from the control output, and a buffer output; and
a capacitor, including a first terminal connected to the second power domain supply node, and a second terminal connected to the buffer output;
wherein the control circuit is configured to provide the control signal including a rising edge a predetermined time after a first supply voltage signal at the first power domain supply node rises above a threshold voltage to raise a voltage at the second terminal of the capacitor to provide a second supply voltage signal at the second power domain supply node.

13. The integrated circuit of claim 1 , wherein the first power domain circuit, the second power domain circuit, the supply circuit and the power management circuit are formed in a single integrated circuit.

14. A power circuit comprising:
a regulator circuit configured to generate a first supply voltage signal at a regulator output;
a switch coupled to the regulator circuit, the switch coupled to a first power domain circuit and a second power domain circuit, the switch having a control node;
a boost circuit; and
a control circuit coupled to the boost circuit and to the control node of the switch, the control circuit configured to selectively cause the switch to disconnect the regulator output from the second power domain circuit based on the regulator output, and to cause the boost circuit to boost a second supply voltage signal for the second power domain circuit.

15. The power circuit of claim 14 , wherein the regulator circuit is configured to regulate a first supply voltage of a first power domain supply node to a value less than a minimum required operating voltage of a non-volatile memory circuit.

16. The power circuit of claim 14 , wherein the regulator circuit is a low dropout regulator.

17. The power circuit of claim 14 , wherein the boost circuit includes:
a buffer circuit, including a buffer input connected to a control output of the control circuit to receive a control signal from the control output, and a buffer output; and
a capacitor, including a first terminal connected to a second power domain supply node of the second power domain circuit, and a second terminal connected to the buffer output;
wherein the control circuit is configured to provide the control signal including a rising edge a predetermined time after the first supply voltage signal rises above a threshold voltage to raise a voltage at the second terminal of the capacitor to provide the second supply voltage signal at the second power domain supply node.

18. A system comprising:
a first power domain circuit comprising a logic circuit, the first power domain circuit having a first power domain supply node;
a second power domain circuit comprising a non-volatile memory circuit, the non-volatile memory circuit coupled to the logic circuit, the second power domain circuit having a second power domain supply node;
a supply circuit having an input and a supply output;
a regulator circuit, having an input coupled to the supply output and a regulator output coupled to the first power domain supply node;
a switch coupled between the first power domain supply node and the second power domain supply node, the switch having a control node;
a boost circuit having a boost output coupled to the second power domain supply node; and
a control circuit, having a control output coupled to the control node of the switch, the control circuit coupled to the boost circuit.

19. The system of claim 18 , wherein the boost circuit includes:
a buffer circuit, including a buffer input connected to the control output to receive a control signal from the control output, and a buffer output; and
a capacitor, including a first terminal connected to

Assignees

• Texas Instruments Inc

Inventors

• Khanna Sudhanshu
• Meng Hao
• Zwerg Michael
• She Christy Leigh
• Bartling Steven Craig

Classifications

• G08C13/02 Primary

  to yield a signal which is a function of two or more signals, e.g. sum or product · CPC title

• G11C11/56

  using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency · CPC title

• G06F1/30

  Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations (for resetting only G06F1/24) · CPC title

• G06F1/26

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• H03K5/24

  the characteristic being amplitude · CPC title