Monotonic counters in memories

Patent metadata

Field	Value
Publication number	US-11056192-B2
Application number	US-201816229609-A
Country	US
Kind code	B2
Filing date	Dec 21, 2018
Priority date	Dec 21, 2018
Publication date	Jul 6, 2021
Grant date	Jul 6, 2021

Abstract

An apparatus, such as a memory (e.g., a NAND memory), can have a controller, a volatile counter coupled to the controller, and a non-volatile memory array coupled to the controller. The controller can be configured to write information, other than a count of the counter, in the array each time the count of the counter has been incremented by a particular number of increments. Counts can be monotonic, non-volatile, and power-loss tolerant.

First claim

What is claimed is:

1. An apparatus, comprising:
a controller;
a volatile counter coupled to the controller; and
a non-volatile memory array coupled to the controller;
wherein the controller is configured to write information, other than a count of the counter, in the array each time the count of the counter has been incremented by a particular number of increments; and
wherein the controller is configured to, at a respective power up of the apparatus:
compute an initialization count by multiplying a quantity of writes of the information up to the power up by the particular number of increments; and
initialize the counter with the initialization count.

2. The apparatus of claim 1 , wherein the controller is configured to
write the information to a respective segment of a quantity of segments of the array during each respective write; and
determine the quantity of writes of the information by counting the segments containing the information.

3. The apparatus of claim 1 , wherein the particular number of increments is greater than one.

4. The apparatus of claim 1 , wherein the controller is configured to increment the count in response to each secure command that is received by the apparatus.

5. The apparatus of claim 4 , wherein the controller is configured to use the count to determine a freshness of the secure command.

6. The apparatus of claim 1 , wherein the non-volatile memory array is a NAND memory array.

7. An apparatus, comprising:
a controller;
a volatile counter coupled to the controller; and
a non-volatile memory array coupled to the controller;
wherein the controller is configured to write information, other than a count of the counter, in the array each time the count of the counter has been incremented by a particular number of increments; and
wherein the array comprises a block comprising:
a plurality of groups of first segments, each respective first segment configured to store the information written during a respective write as respective first information; and
a plurality of second segments, each respective second segment pointing to a respective group of the first segments and configured to store second information to indicate that at least one of the first segments of the respective group of first segments is available to store the respective first information.

8. The apparatus of claim 7 , wherein the controller is configured to write the second information to a respective second segment in response to determining that a respective group of first segments pointed to by a preceding second segment is full.

9. The apparatus of claim 8 , wherein
the second information comprises a first bit pattern; and
the controller is configured to write a second bit pattern to the preceding second segment in response to determining that the respective group of first segments pointed to by the preceding second segment is full.

10. The apparatus of claim 7 , wherein the controller is configured to
locate a second segment to which the second information is last written; and
write the respective first information in a first segment in the respective group of first segments to which the located second segment points.

11. The apparatus of claim 7 , wherein the controller is configured to
determine, during a power up of the apparatus, that a power loss occurred while the second information is written to a respective second segment pointing to a respective group of first segments in response to determining, during the power up of the apparatus, that the respective second segment contains corrupted information;
replace the corrupted information with third information; and
program the second information to a second segment following the respective second segment with the third information and pointing to a respective group of first segments following the respective group of first segments pointed to by the respective second segment that contained the corrupted information.

12. The apparatus of claim 7 , wherein each of the groups of first segments comprises a page of memory cells of the block of memory cells of the non-volatile memory array.

13. An apparatus, comprising:
a controller;
a volatile counter coupled to the controller; and
a non-volatile memory array coupled to the controller;
wherein the controller is configured to write information, other than a count of the counter, in the array each time the count of the counter has been incremented by a particular number of increments;
wherein the memory array comprises a quantity of segments, each respective segment initially storing a first bit pattern; and
wherein the controller is further configured to:
write a second bit pattern in a particular segment of the quantity of segments initially storing the first bit pattern to indicate that the controller is to write the information to the particular segment a next time the count of the counter has been incremented by the particular quantity of increments; and
write the information to the particular segment by writing a third bit pattern to the particular segment storing the second bit pattern the next time the count of the counter has been incremented by the particular quantity of increments.

14. The apparatus of claim 13 , wherein
the first bit pattern comprises a plurality of bits having a first bit value;
the controller is configured to:
write the second bit pattern in the particular segment by writing a portion the plurality of the bits having the first bit value to a second bit value so that the second bit pattern comprises a plurality of bits having the first bit value and a plurality of bits having the second bit value; and
write the information to the particular segment by writing the third bit pattern to the particular segment having the second bit pattern comprises the controller being configured to write the plurality of bits having the first bit value in the second bit pattern to the second bit value.

15. An apparatus, comprising:
a controller;
a volatile counter coupled to the controller; and
first and second blocks of non-volatile memory cells coupled to the controller;
wherein
one of the first and second blocks is configured to have an active status while the other of the first and second blocks has an inactive status;
each of the first and second blocks comprises a first region configured to store a first quantity of count-milestone records and a second region configured to store a second quantity of block-milestone records;
the controller is configured to:
swap the respective statuses of the blocks in response to the first region of the block having the active status having the quantity of count-milestone records
write the block-milestone record in the second region of the block that becomes the block having the active status in response to the swap; and
write the count-milestone record in the first region of the block having the active status each time the count of the counter has been incremented by a particular number of increments.

16. The apparatus of claim 15 , wherein the controller is configured to, at a respective power up of the apparatus:
determine a first count contribution by multiplying the particular number of increments by a number of the count-milestone records in the first region of the block having the active status at the respective power up of the apparatus;
determine a second count contribution by multiplying the particular number of increments by the first quantity of the count-milestone records and by a number of the block-milestone records in the second region of the block having the act

Assignees

• Micron Technology Inc

Inventors

• Mondello Antonino
• Tomaiuolo Francesco
• Condemi Carmelo
• Zerilli Tommaso

Classifications

• G11C16/22

  Safety or protection circuits preventing unauthorised or accidental access to memory cells · CPC title

• G11C13/0059

  Security or protection circuits or methods · CPC title

• G11C7/24

  Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells · CPC title

• G11C7/20

  Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory · CPC title

• G06F21/79

  in semiconductor storage media, e.g. directly-addressable memories · CPC title