Conditional transaction end instruction

Patent metadata

Field	Value
Publication number	US-9454370-B2
Application number	US-201414212004-A
Country	US
Kind code	B2
Filing date	Mar 14, 2014
Priority date	Mar 14, 2014
Publication date	Sep 27, 2016
Grant date	Sep 27, 2016

Abstract

A Conditional Transaction End (CTEND) instruction is provided that allows a program executing in a nonconstrained transactional execution mode to inspect a storage location that is modified by either another central processing unit or the Input/Output subsystem. Based on the inspected data, transactional execution may be ended or aborted, or the decision to end/abort may be delayed, e.g., until a predefined event occurs. For instance, when the instruction executes, the processor is in a nonconstrained transaction execution mode, and the transaction nesting depth is one at the beginning of the instruction, a second operand of the instruction is inspected, and based on the inspected data, transaction execution may be ended or aborted, or the decision to end/abort may be delayed, e.g., until a predefined event occurs, such as the value of the second operand becomes a prespecified value or a time interval is exceeded.

First claim

What is claimed is:

1. A computer program product for executing a machine instruction in a computing environment, said computer program product comprising:
a computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
obtaining, by a processor, the machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising:
an operation code to specify a conditional transaction end operation; and
one or more fields to provide a location of an operand; and

executing, by the processor, the machine instruction, the executing comprising:
fetching the operand from the location;
based on the operand comprising a first value, aborting transactional execution of a transaction associated with the machine instruction;
based on the operand comprising a second value, ending the transaction; and
based on the operand comprising a third value, delaying completion of the machine instruction until a predefined action occurs.

2. The computer program product of claim 1 , wherein the operand is stored by another processor or an input/output subsystem coupled to the processor.

3. The computer program product of claim 1 , wherein the predefined action comprises one of:
the operand becomes the first value or the second value; or
an interval of time has been exceeded.

4. The computer program product of claim 3 , wherein the interval of time is exceeded, and wherein the executing further comprises:
aborting transactional execution of the transaction; and
setting a condition code in a transaction abort program status word to a defined value.

5. The computer program product of claim 1 , wherein the first value comprises a negative value, the second value comprises zero, and the third value comprises a positive value.

6. The computer program product of claim 1 , wherein based on aborting transactional execution, a condition code in a transaction abort program status word is set to a defined value.

7. The computer program product of claim 1 , wherein based on ending the transaction, store accesses made by the transaction are committed, a transaction nesting depth is set to zero, the processor exits transactional execution mode, and a condition code is set to a defined value.

8. The computer program product of claim 1 , wherein the executing further comprises:
determining whether the processor is in a nonconstrained transactional execution mode;
determining whether a transaction nesting depth is of a predefined value; and
based on the processor being in the nonconstrained transactional execution mode and the transaction nesting depth being of the predefined value, fetching the operand from the location.

9. The computer program product of claim 8 , wherein the predefined value of the transaction nesting depth comprises one.

10. The computer program product of claim 1 , wherein the one or more fields comprise an index field, a base field, a first displacement field and a second displacement field, wherein contents of registers designated by one or more of the index field and the base field are added to a concatenation of the second displacement field and the first displacement field to provide the location of the operand.

11. The computer program product of claim 10 , wherein the operand is a second operand of the instruction, and comprises a 64-bit signed binary integer.

12. A computer system for executing a machine instruction in a computing environment, said computer system comprising:
a memory; and
a processor in communications with the memory, wherein the computer system is configured to perform a method, said method comprising:
obtaining, by the processor, the machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising:
an operation code to specify a conditional transaction end operation; and
one or more fields to provide a location of an operand; and

executing, by the processor, the machine instruction, the executing comprising:
fetching the operand from the location;
based on the operand comprising a first value, aborting transactional execution of a transaction associated with the machine instruction;
based on the operand comprising a second value, ending the transaction; and
based on the operand comprising a third value, delaying completion of the machine instruction until a predefined action occurs.

13. The computer system of claim 12 , wherein the predefined action comprises one of:
the operand becomes the first value or the second value; or
an interval of time has been exceeded.

14. The computer system of claim 13 , wherein the interval of time is exceeded, and wherein the executing further comprises:
aborting transactional execution of the transaction; and
setting a condition code in a transaction abort program status word to a defined value.

15. The computer system of claim 12 , wherein based on ending the transaction, store accesses made by the transaction are committed, a transaction nesting depth is set to zero, the processor exits transactional execution mode, and a condition code is set to a defined value.

16. The computer system of claim 12 , wherein the executing further comprises:
determining whether the processor is in a nonconstrained transactional execution mode;
determining whether a transaction nesting depth is of a predefined value; and
based on the processor being in the nonconstrained transactional execution mode and the transaction nesting depth being of the predefined value, fetching the operand from the location.

17. The computer system of claim 12 , wherein the one or more fields comprise an index field, a base field, a first displacement field and a second displacement field, wherein contents of registers designated by one or more of the index field and the base field are added to a concatenation of the second displacement field and the first displacement field to provide the location of the operand.

Assignees

• IBM

Inventors

• Greiner Dan F
• Jacobi Christian
• Mitran Marcel
• Schmidt Donald W
• Slegel Timothy J

Classifications

• G06F9/467

  Transactional memory (G06F9/528 takes precedence) · CPC title

• G06F9/3834

  Maintaining memory consistency · CPC title

• G06F9/30072 Primary

  to perform conditional operations, e.g. using predicates or guards · CPC title

• G06F9/30047 Primary

  Prefetch instructions; cache control instructions · CPC title

• G06F9/30076

  to perform miscellaneous control operations, e.g. NOP · CPC title