Compare and delay instructions

Patent metadata

Field	Value
Publication number	US-2015261529-A1
Application number	US-201414212378-A
Country	US
Kind code	A1
Filing date	Mar 14, 2014
Priority date	Mar 14, 2014
Publication date	Sep 17, 2015
Grant date	—

Abstract

A delay facility is provided in which program execution may be delayed until a predefined event occurs, such as a comparison of memory locations results in a true condition, a timeout is reached, an interruption is made pending or another condition exists. The delay facility includes one or more compare and delay machine instructions used to delay execution. The one or more compare and delay instructions may include a 32-bit compare and delay (CAD) instruction and a 64-bit compare and delay (CADG) instruction.

First claim

1 . A computer program product for executing a machine instruction in a computing environment, said computer program product comprising:
a computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
obtaining, by a processor, a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising:
an operation code to specify a compare and delay operation;
one or more first fields to be used to obtain a first operand; and
one or more second fields to be used to obtain a second operand; and

executing, by the processor, the machine instruction, the executing comprising:
comparing the first operand and the second operand to obtain a comparison result;
determining whether a mask indicator corresponding to the comparison result is set to a defined value; and
based on determining that the mask indicator corresponding to the comparison result is set to the defined value, delaying completion of the machine instruction until occurrence of a predefined event.

2 . The computer program product of claim 1 , wherein based on determining that the mask indicator corresponding to the comparison result is not set to the defined value, completing the machine instruction.

3 . The computer program product of claim 1 , wherein the one or more first fields to be used to obtain the first operand comprise a register field, the register field comprising a designation of a register, the register comprising the first operand, and wherein the one or more second fields to be used to obtain the second operand comprise a base field, a first displacement field and a second displacement field, wherein contents of a register specified in the base field are added to a concatenation of the second displacement field and the first displacement field to provide an address of the second operand in memory.

4 . The computer program product of claim 1 , wherein the machine instruction further comprises a mask field, the mask field comprising the mask indicator.

5 . The computer program product of claim 4 , wherein the comparison result comprises one of equal, the first operand less than the second operand, or the first operand greater than the second operand, and wherein the mask field comprises a first mask indicator for equal, a second mask indicator for the first operand less than the second operand, and a third mask indicator for the first operand greater than the second operand, and wherein the mask indicator is one of the first mask indicator, the second mask indicator or the third mask indicator depending on the comparison result.

6 . The computer program product of claim 1 , wherein the second operand is monitored during the delaying completion of the machine instruction, and wherein the predefined event comprises determining that the mask indicator corresponding to the comparison result resulting from another comparison of the first operand and the second operand is not set to the defined value.

7 . The computer program product of claim 1 , wherein the predefined event comprises an enabled interruption is made pending.

8 . The computer program product of claim 1 , wherein the predefined event comprises reaching a predefined limit or occurrence of a selected processor condition.

9 . The computer program product of claim 1 , wherein the second operand is located in a memory location shared by the processor and at least one of another processor and an input/output subsystem, the second operand stored by the another processor or the input/output subsystem.

10 . The computer program product of claim 1 , wherein the method further comprises determining whether the machine instruction is authorized to be executed in a non-privileged state based on the processor not being in a supervisor state, and performing the comparing the first operand and the second operand based on the determining indicating the machine instruction is authorized to be executed in the non-privileged state when the processor is not in the supervisor state.

11 . The computer program product for claim 1 , wherein the method further comprises determining a condition code for the machine instruction, the determining the condition code using the comparison result, wherein for a comparison result of equal, the condition code is a first value; for a comparison result of the first operand less than the second operand, the condition code is a second value; and for a comparison result of the first operand greater than the second operand, the condition code is a third value.

12 . A computer system for executing a machine instruction in a computing environment, said computer system comprising:
a memory; and a processor in communications with the memory, wherein the computer system is configured to perform a method, said method comprising:
obtaining, by the processor, a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising:
an operation code to specify a compare and delay operation;
one or more first fields to be used to obtain a first operand; and
one or more second fields to be used to obtain a second operand; and

executing, by the processor, the machine instruction, the executing comprising:
comparing the first operand and the second operand to obtain a comparison result;
determining whether a mask indicator corresponding to the comparison result is set to a defined value; and
based on determining that the mask indicator corresponding to the comparison result is set to the defined value, delaying completion of the machine instruction until occurrence of a predefined event.

13 . The computer system of claim 12 , wherein the machine instruction further comprises a mask field, the mask field comprising the mask indicator.

14 . The computer system of claim 13 , wherein the comparison result comprises one of equal, the first operand less than the second operand, or the first operand greater than the second operand, and wherein the mask field comprises a first mask indicator for equal, a second mask indicator for the first operand less than the second operand, and a third mask indicator for the first operand greater than the second operand, and wherein the mask indicator is one of the first mask indicator, the second mask indicator or the third mask indicator depending on the comparison result.

15 . The computer system of claim 12 , wherein the predefined event comprises one of: determining that the mask indicator corresponding to the comparison result resulting from another comparison of the first operand and the second operand is not set to the defined value; an enabled interruption is made pending; reaching a predefined limit; or occurrence of a selected processor condition.

16 . The computer system of claim 12 , wherein the method further comprises determining whether the machine instruction is authorized to be executed in a non-privileged state based on the processor not being in a supervisor state, and performing the comparing the first operand and the second operand based on the determining indicating the machine instruction is authorized to be executed in the non-privileged state when the processor is not in the supervisor state.

17 . The computer system for claim 12 , wherein the method further comprises determining a condition code for the machine instruction, the determining the condition code using the

Assignees

• IBM

Inventors

• Gainey Jr Charles W
• Greiner Dan F
• Jacobi Christian
• Mitran Marcel
• Schmidt Donald W
• Slegel Timothy J

Classifications

• G06F9/30065 Primary

  Loop control instructions; iterative instructions, e.g. LOOP, REPEAT · CPC title

• G06F9/3005

  to perform operations for flow control · CPC title

• G06F9/30021 Primary

  Compare instructions, e.g. Greater-Than, Equal-To, MINMAX · CPC title

• G06F9/3851

  from multiple instruction streams, e.g. multistreaming · CPC title

• G06F9/455

  Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines · CPC title