Apparatus, method, and system for providing a decision mechanism for conditional commits in an atomic region

Patent metadata

Field	Value
Publication number	US-9146844-B2
Application number	US-201313893238-A
Country	US
Kind code	B2
Filing date	May 13, 2013
Priority date	Sep 25, 2010
Publication date	Sep 29, 2015
Grant date	Sep 29, 2015

Abstract

An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.

First claim

What is claimed is:

1. A computing device to optimize program code, the computing device comprising:
a compiler hardware module to: (i) identify a section of program code to be optimized, (ii) demarcate at least a portion of the section of program code as an atomic region in response to identification of the section of program code to be optimized, (iii) insert speculative checkpoint code at a speculative checkpoint determined to be within the atomic region, and (iv) optimize the section of program code in response to identification of the section of program code to be optimized; and
a decode hardware module to determine the speculative checkpoint within the atomic region.

2. The computing device of claim 1 , wherein to demarcate at least a portion of the section of program code as an atomic region comprises to: (i) insert a start transaction instruction at a beginning of the portion of the section of code, and (ii) insert an end transaction instruction at an end of the portion of the section of code.

3. The computing device of claim 1 , wherein the speculative checkpoint code includes a speculative checkpoint operation to: (i) checkpoint a speculative register file in a speculative checkpoint register file, and (ii) checkpoint a store buffer in a speculative cache; and
wherein the compiler hardware module further to insert fix-up code to roll-back to the checkpoint of the speculative register file held in the speculative checkpoint register file in response to the speculative cache or the store buffer running out of resources during execution of the portion of the section of code.

4. The computing device of claim 3 , wherein to insert fix-up code in response to the store buffer running out of resources during execution of the portion of the section of code comprises to insert fix-up code in response to the store buffer not including any available entries during execution of the portion of the section of code; and
wherein to insert fix-up code in response to the speculative cache running out of resources during execution of the portion of the section of code comprises to insert fix-up code in response to the speculative cache not including enough available entries to hold entries from the store buffer upon execution of the speculative checkpoint operation by the computing device.

5. The computing device of claim 1 , wherein to optimize the section of program code comprises to optimize the section of code via an optimization technique selected from a group consisting of Partial Redundancy Load Elimination (PRLE), Partial Dead Store Elimination (PDSE), loop optimization, data-flow optimization, code generation optimization, bounds checking elimination, branch offset optimization, dead code elimination, and jump threading.

6. A non-transitory, machine readable medium comprising a plurality of instructions stored thereon that in response to being executed by a computing device, cause the computing device to:
identify a section of program code to be optimized;
demarcate at least a portion of the section of program code as an atomic region in response to identification of the section of program code to be optimized;
determine a speculative checkpoint within the atomic region;
insert speculative checkpoint code at the a speculative checkpoint in response to determination of the speculative checkpoint; and
optimize the section of program code in response to identification of the section of program code to be optimized.

7. The non-transitory, machine readable medium of claim 6 , wherein to demarcate at least a portion of the section of program code as an atomic region comprises to: (i) insert a start transaction instruction at a beginning of the portion of the section of code, and (ii) insert an end transaction instruction at an end of the portion of the section of code.

8. The non-transitory, machine readable medium of claim 6 , wherein the speculative checkpoint code includes a speculative checkpoint operation, which when executed, causes the computing device to: (i) checkpoint a speculative register file in a speculative checkpoint register file, and (ii) checkpoint a store buffer in a speculative cache; and
wherein the plurality of instructions further cause the computing device to insert fix-up code to roll-back to the checkpoint of the speculative register file held in the speculative checkpoint register file in response to the speculative cache or the store buffer running out of resources during execution of the portion of the section of code.

9. The non-transitory, machine readable medium of claim 8 , wherein to insert fix-up code in response to the store buffer running out of resources during execution of the portion of the section of code comprises to insert fix-up code in response to the store buffer not including any available entries during execution of the portion of the section of code; and
wherein to insert fix-up code in response to the speculative cache running out of resources during execution of the portion of the section of code comprises to insert fix-up code in response to the speculative cache not including enough available entries to hold entries from the store buffer upon execution of the speculative checkpoint operation by the computing device.

10. The non-transitory, machine readable medium of claim 8 , wherein to optimize the section of program code comprises to optimize the section of code via an optimization technique selected from a group consisting of Partial Redundancy Load Elimination (PRLE), Partial Dead Store Elimination (PDSE), loop optimization, data-flow optimization, code generation optimization, bounds checking elimination, branch offset optimization, dead code elimination, and jump threading.

11. A method for optimizing program code, the method comprising:
identifying, by a computing device, a section of program code to be optimized;
demarcating, by the computing device, at least a portion of the section of program code as an atomic region in response to identifying the section of program code to be optimized;
determining, by the computing device, a speculative checkpoint within the atomic region;
inserting, by the computing device, speculative checkpoint code at the a speculative checkpoint in response to determining the speculative checkpoint; and
optimizing, by the computing device, the section of program code in response to identifying the section of program code to be optimized.

12. The method of claim 11 , wherein demarcating at least a portion of the section of program code as an atomic region comprises: (i) inserting a start transaction instruction at a beginning of the portion of the section of code, and (ii) inserting an end transaction instruction at an end of the portion of the section of code.

13. The method of claim 11 , further comprising:
executing, by the computing device, the speculative checkpoint operation;
checkpointing, by the computing device, a speculative register file in a speculative checkpoint register file in response to executing the speculative checkpoint operation;
checkpointing, by the computing device, a store buffer in a speculative cache in response to executing the speculative checkpoint operation; and
inserting, by the computing device, fix-up code to roll-back to the checkpoint of the speculative register file held in the speculative checkpoint register file in response to the speculative cache or the store buffer running out of resources during execution of the portion of the section of code.

14. The method of claim 13 , wherein inserting fix-up code in response to the store buffer running out of resources during execution of the portion of the sect

Assignees

• Intel Corp

Inventors

• Breternitz Mauricio
• Wu Youfeng
• Wang Cheng
• Borin Edson
• Hu Shiliang
• Zilles Craig B

Classifications

• G06F9/3004

  to perform operations on memory · CPC title

• G06F9/3842

  Speculative instruction execution · CPC title

• G06F9/30087

  Synchronisation or serialisation instructions · CPC title

• G06F9/30116

  Shadow registers, e.g. coupled registers, not forming part of the register space · CPC title

• G06F11/3688 Primary

  for test execution, e.g. scheduling of test suites · CPC title