Manufacturing method of semiconductor device and semiconductor manufacturing apparatus

Patent metadata

Field	Value
Publication number	US-9448065-B2
Application number	US-201514636081-A
Country	US
Kind code	B2
Filing date	Mar 2, 2015
Priority date	Sep 16, 2014
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

A method for manufacturing a semiconductor device includes determining a position of a first semiconductor chip having a plurality of first electrodes, using one or more first alignment marks formed on the first semiconductor chip, determining a position of a second semiconductor chip having a plurality of second electrodes, using one or more second alignment marks formed on the second semiconductor chip, moving the second semiconductor chip relative to the first semiconductor chip, based on the determined positions of the first and second semiconductor chips, such that the second electrodes are aligned with the first electrodes, after said moving, stacking the second semiconductor chip on the first semiconductor chip, such that the first electrodes are electrically connected to the second electrodes, and calculating a misalignment amount between the first semiconductor chip and the second semiconductor chip stacked thereon.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, comprising:
determining a position of a first semiconductor chip having a plurality of first electrodes, using one or more first alignment marks formed on the first semiconductor chip;
determining a position of a second semiconductor chip having a plurality of second electrodes, using one or more second alignment marks formed on the second semiconductor chip;
moving the second semiconductor chip relative to the first semiconductor chip, based on the determined positions of the first and second semiconductor chips, such that the second electrodes are aligned with the first electrodes;
after said moving, stacking the second semiconductor chip on the first semiconductor chip, such that the first electrodes are electrically connected to the second electrodes;
after said stacking, determining an after-stacking position of the second semiconductor chip, using one or more third alignment marks formed on a surface of the second semiconductor chip opposite to a surface on which the one or more second alignment marks are formed; and
calculating, by a control unit, a misalignment amount between the first semiconductor chip and the second semiconductor chip stacked thereon, based on the position of the first semiconductor chip before said stacking and the after-stacking position of the second semiconductor chip after the said stacking.

2. The method according to claim 1 , wherein
the position of the first semiconductor chip is determined when the first semiconductor chip is placed on a stage such that the first electrodes face the second semiconductor chip, and
the position of the second semiconductor chip is determined while the second semiconductor chip is held in a holder and moved with respect to the first semiconductor chip.

3. The method according to claim 1 , wherein
the position of the first semiconductor chip is determined based on an image of the first semiconductor chip including the one or more first alignment marks, and
the position of the second semiconductor chip is determined based on an image of the second semiconductor chip including the one or more second alignment marks.

4. The method according to claim 1 , further comprising:
determining whether or not the misalignment amount is within a predetermined range.

5. The method according to claim 4 , further comprising:
stacking a third semiconductor chip on the second semiconductor chip, when the misalignment is determined to be within the predetermined range.

6. The method according to claim 5 , further comprising:
calculating a misalignment amount between the second semiconductor chip and the third semiconductor chip stacked thereon.

7. The method according to claim 5 , further comprising:
when the misalignment is determined to be within the predetermined range,
determining a position of the third semiconductor chip, using one or more third alignment marks formed on the third semiconductor chip;
moving the third semiconductor chip relative to the second semiconductor chip, based on the determined position of the second and third semiconductor chips, such that third electrodes formed on third semiconductor chip are aligned with fourth electrodes formed on the second semiconductor chip, wherein
the stacking of the third semiconductor chip is carried out after moving the third semiconductor chip, such that the third electrodes are electrically connected to the fourth electrodes.

8. The method according to claim 7 , wherein
the third semiconductor chip is moved to a position such that the misalignment amount between the second and third semiconductor chips offsets the misalignment amount between the first and second semiconductor chips.

9. The method according to claim 7 , wherein
the third semiconductor chip is moved to a position at which there is no misalignment between the first and third semiconductor chips.

10. The method according to claim 1 , wherein
the first and second electrodes are conductive bumps.

11. A semiconductor manufacturing apparatus comprising:
a stage on which a first semiconductor chip is to be placed;
a holder configured to hold a second semiconductor chip that is to be stacked on the first semiconductor chip placed on the stage;
an image capturing unit configured to capture a first image of the first semiconductor chip on the stage before the second semiconductor chip is stacked thereon, the first image including one or more first alignment marks formed on the first semiconductor chip, and a second image of the second semiconductor chip in the holder before stacking on the first semiconductor chip, the second image including one or more second alignment marks formed on the second semiconductor chip; and
a control unit configured to:
cause the holder to move relative to the stage, such that the second semiconductor chip can be stacked on the first semiconductor chip,
calculate a first misalignment amount between the first semiconductor chip and the second semiconductor chip stacked thereon, based on the first and second images,
determine whether or not the first misalignment amount is within a predetermined range,
cause the holder move relative to the stage to stack the second semiconductor chip on the first semiconductor when the first misalignment amount is within the predetermined range,
cause the image capturing unit to capture a third image of the second semiconductor chip stacked on the first semiconductor chip and including one or more third alignment marks formed on a surface of the second semiconductor chip opposite to a surface on which the one or more second alignment marks are formed, and
calculate a second misalignment amount between the first semiconductor chip and the second semiconductor chip based on the first and third images.

12. The semiconductor manufacturing apparatus according to claim 11 , wherein
the control unit is further configured to cause an alarm to be generated when the first misalignment amount is determined to be greater than the predetermined range.

13. The semiconductor manufacturing apparatus according to claim 11 , wherein
the control unit is further configured to calculate a correction value to be used for stacking of a third semiconductor chip, based on the first misalignment amount, when the first misalignment amount is determined to be within the predetermined range.

14. The semiconductor manufacturing apparatus according to claim 13 , wherein
the control unit is further configured to position the third semiconductor chip for stacking on the second semiconductor chip according to the correction value.

15. The semiconductor manufacturing apparatus according to claim 11 , wherein the control unit is further configured to position a third semiconductor chip for stacking on the second semiconductor chip according to a correction value calculated based on the second misalignment amount.

16. The semiconductor manufacturing apparatus according to claim 11 , wherein the control unit is further configured to position a third semiconductor chip for stacking on the second semiconductor chip according to a correction value calculated based on the first misalignment amount.

Assignees

• Toshiba Kk

Inventors

• Fukayama Shinya
• Oyama Yukifumi
• Murakami Kazuhiro

Classifications

• H10W46/301

  for alignment · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W72/07231

  Techniques · CPC title

• H10W72/072

  of bump connectors · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title