Analogue-to-digital conversion circuitry

Patent metadata

Field	Value
Publication number	US-9444479-B2
Application number	US-201414553598-A
Country	US
Kind code	B2
Filing date	Nov 25, 2014
Priority date	Jan 26, 2009
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line.

First claim

What is claimed is:

1. An analogue-to-digital conversion circuit, comprising:
a first node configured to receive an input current signal;
a plurality of first switch circuits including a plurality of first terminals and a plurality of second terminals, each of the plurality of first terminals being coupled to the first node, the plurality of first switch circuits being configured to sample the input current signal in accordance with a plurality of sinusoidal control signals and generate a plurality of sample current signals; and
a plurality of analogue-to-digital converters coupled to the plurality of second terminals and configured to convert the plurality of sample current signals and generate a plurality of converted signals.

2. The analogue-to-digital conversion circuit of claim 1 ,
wherein the plurality of first switch circuits are configured to be sequentially selected during corresponding ones of a plurality of selection periods which occur in succession, successive selection periods of the plurality of selection periods being partially overlapped.

3. The analogue-to-digital conversion circuit of claim 2 ,
wherein the selection periods of the plurality of selection periods which occur in non-succession are non-overlapped.

4. The analogue-to-digital conversion circuit of claim 2 , further comprising:
a reset circuit configured to bring a voltage potential of at least one of the plurality of second terminals to a particular value at a time between successive selection periods for the at least one first switch circuit.

5. The analogue-to-digital conversion circuit of claim 1 , further comprising:
a digital circuit configured to generate a digital output signal on the basis of the plurality of converted signals.

6. The analogue-to-digital conversion circuit of claim 1 , further comprising:
a plurality of demultiplexers coupled between the plurality of second terminals and the plurality of analogue-to-digital converters, each of the plurality of demultiplexers being configured to demultiplex a corresponding one of the plurality of sample current signals and generate a plurality of demultiplexed current signals,
wherein each of the plurality of analogue-to-digital converters is configured to convert the plurality of demultiplexed current signals and generate a corresponding one of the plurality of converted signals.

7. The analogue-to-digital conversion circuit of claim 6 ,
wherein each of the plurality of demultiplexers includes a plurality of second switch circuits configured to generate the plurality of demultiplexed current signals on the basis of the corresponding one of the plurality of sample current signals.

8. The analogue-to-digital conversion circuit of claim 1 , further comprising:
a calibration circuit configured to calibrate characteristics of the plurality of first switch circuits on the basis of the plurality of converted signals.

Assignees

• Socionext Inc

Inventors

• Dedic Ian Juso
• Allen Gavin Lambertus

Classifications

• H03M1/1009

  Calibration · CPC title

• H03L7/091

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• Y10T307/76

  Cross-Sectional Technologies · mapped topic

• H03M1/121

  Interleaved, i.e. using multiple converters or converter parts for one channel · CPC title