TiOx based selector element

Patent metadata

Field	Value
Publication number	US-9443906-B2
Application number	US-201314136365-A
Country	US
Kind code	B2
Filing date	Dec 20, 2013
Priority date	Dec 20, 2013
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

Control elements that can be suitable for nonvolatile memory device applications are disclosed. The control element can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. The control element can be based on a single dielectric layer or on a multilayer dielectric stack.

First claim

What is claimed is:

1. A nonvolatile memory cell comprising:
a first electrode;
a second electrode;
a resistive switching layer comprising a first dielectric layer and configured to change a resistance between a low resistive state and a high resistive state; and
a control element comprising a second dielectric layer, a third dielectric layer, and a fourth dielectric layer such that the second dielectric layer is disposed between the third dielectric layer and the fourth dielectric layer,
wherein the fourth dielectric layer and the third dielectric layer comprise a same material,
wherein the control element and the resistive switching layer are disposed between the first electrode and the second electrode and connected in series with each other and with the first electrode and the second electrode;
wherein the control element is to control a flow of an electrical current between the first electrode and the second electrode and through the resistive switching layer while the resistive switching layer changes the resistance between the low resistive state and the high resistive state,
wherein the first electrode and the second electrode are used for addressing the resistive switching layer without any intervening electrodes connected to the control element and the resistive switching layer between the first electrode and the second electrode;
wherein the control element has a non-linear current-voltage response,
wherein the second dielectric layer comprises titanium oxide, and
wherein the second dielectric layer further comprises a dopant.

2. The nonvolatile memory cell as in claim 1 , wherein the dopant comprises vanadium.

3. The nonvolatile memory cell as in claim 2 , wherein a concentration of the vanadium in the second dielectric layer is between 0 atomic % and 3 atomic %.

4. The nonvolatile memory cell as in claim 2 , wherein a concentration of the vanadium in the second dielectric layer is between 15 atomic % and 25 atomic %.

5. The nonvolatile memory cell as in claim 2 , wherein a concentration of the vanadium in the second dielectric layer is between 19 atomic % and 23 atomic %.

6. The nonvolatile memory cell as in claim 1 , wherein a thickness of the second dielectric layer is between 5 nm and 15 nm.

7. The nonvolatile memory cell as in claim 1 , wherein the second dielectric layer comprises titanium oxide having a thickness between 5 nm and 15 nm, wherein the dopant comprises vanadium, and wherein a concentration of the vanadium in the second dielectric layer is between 0 atomic % and 3 atomic %.

8. The nonvolatile memory cell as in claim 1 , wherein the second dielectric layer has a thickness between 5 nm and 15 nm, wherein the dopant comprises vanadium, and wherein a concentration of the vanadium in the second dielectric layer is between 15 atomic % and 25 atomic %.

9. The nonvolatile memory cell as in claim 1 , wherein the second dielectric layer dielectric layer has a thickness between 5 nm and 15 nm, wherein the dopant comprises vanadium, and wherein a concentration of the vanadium in the second dielectric layer is between 19 atomic % and 23 atomic %.

10. The nonvolatile memory cell as in claim 1 , wherein each of the fourth dielectric layer and the third dielectric layer comprises tantalum oxide.

11. The nonvolatile memory cell as in claim 10 , wherein a thickness of each of the fourth dielectric layer and the third dielectric layer is between 1 nm and 5 nm.

12. The nonvolatile memory cell as in claim 1 , wherein a thickness of the second dielectric layer is between 0.1 nm and 5 nm.

13. The nonvolatile memory cell as in claim 1 ,
wherein each of the fourth dielectric layer and the third dielectric layer comprises tantalum oxide,
wherein a thickness of each of the first dielectric layer and the third dielectric layer is between 1 nm and 5 nm, and
wherein a thickness of the second dielectric layer is between 0.1 nm and 5 nm.

14. The nonvolatile memory cell as in claim 1 , wherein the control element is a unipolar selector.

15. The nonvolatile memory cell as in claim 1 , wherein the control element is a bipolar selector.

16. The nonvolatile memory cell as in claim 1 , wherein the second dielectric layer has a graded band gap.

17. The nonvolatile memory cell as in claim 1 , wherein the dopant for the second dielectric layer is selected to increase a leakage current of the second dielectric layer due to trap-assisted conduction mechanisms in the second dielectric layer.

18. The nonvolatile memory cell as in claim 1 , wherein the control element further comprises a first metal layer and a second metal layer such as a stack of the third dielectric layer, the second dielectric layer, and the fourth dielectric layer is disposed between the first metal layer and the second metal layer, wherein the first metal layer and the second metal layer have same composition.

19. The nonvolatile memory cell as in claim 18 , wherein the first metal layer and the second metal layer comprise titanium nitride.

Assignees

• Intermolecular Inc

Inventors

• Mathur Monica Sawkar
• Ananthan Venkat
• Clark Mark
• Phatak Prashant B

Classifications

• H01L45/00

  Electricity · mapped topic

• H01L27/2463

  Electricity · mapped topic

• H01L45/08

  Electricity · mapped topic

• H01L27/2418 Primary

  Electricity · mapped topic

• H10B63/22 Primary

  of the metal-insulator-metal type · CPC title