Semiconductor device and method of forming a thin wafer without a carrier

Patent metadata

Field	Value
Publication number	US-9443762-B2
Application number	US-201313933406-A
Country	US
Kind code	B2
Filing date	Jul 2, 2013
Priority date	Mar 26, 2009
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

A semiconductor device has a conductive via in a first surface of a substrate. A first interconnect structure is formed over the first surface of the substrate. A first bump is formed over the first interconnect structure. The first bump is formed over or offset from the conductive via. An encapsulant is deposited over the first bump and first interconnect structure. A portion of the encapsulant is removed to expose the first bump. A portion of a second surface of the substrate is removed to expose the conductive via. The encapsulant provides structural support and eliminates the need for a separate carrier wafer when thinning the substrate. A second interconnect structure is formed over the second surface of the substrate. A second bump is formed over the first bump. A plurality of semiconductor devices can be stacked and electrically connected through the conductive via.

First claim

What is claimed:

1. A semiconductor device, comprising:
a substrate;
a conductive via formed through the substrate;
an encapsulant deposited over a first surface of the substrate;
a first bump disposed in the encapsulant, wherein a surface of the first bump is coplanar with a surface of the encapsulant;
a first interconnect structure contacting a surface of the first bump over the first surface of the substrate; and
a second bump formed over or laterally offset from a surface of the conductive via opposite the first surface of the substrate.

2. The semiconductor device of claim 1 , further comprising a second bump disposed directly on the coplanar surface of the first bump.

3. The semiconductor device of claim 1 , wherein the conductive via protrudes from a second surface of the substrate opposite the first surface of the substrate.

4. The semiconductor device of claim 1 , further including a second interconnect structure formed between the first bump and conductive via.

5. The semiconductor device of claim 1 , further including a second interconnect structure formed between the conductive via and second bump.

6. The semiconductor device of claim 1 , further including a plurality of stacked semiconductor devices electrically connected through the conductive via.

7. A semiconductor device, comprising:
a substrate;
a conductive via formed in a first surface of the substrate and protruding from a second surface of the substrate opposite the first surface of the substrate;
an encapsulant deposited over the first surface of the substrate;
a first bump disposed in the encapsulant; and
an interconnect structure formed between the conductive via and first bump.

8. The semiconductor device of claim 7 , further including a second bump formed over or laterally offset from a surface of the conductive via opposite the first surface of the substrate.

9. The semiconductor device of claim 7 , further including an interconnect structure formed over the first bump.

10. The semiconductor device of claim 7 , wherein a surface of the first bump is coplanar with a surface of the encapsulant.

11. The semiconductor device of claim 7 , further including a plurality of stacked semiconductor devices electrically connected through the conductive via.

12. The semiconductor device of claim 10 , further including a second bump disposed directly on the coplanar surface of the first bump.

13. A semiconductor device, comprising:
a substrate;
an encapsulant deposited over the substrate;
a bump disposed in the encapsulant with an interior arcuate surface portion proximate to the substrate and an exterior surface portion, wherein a surface of the encapsulant is coplanar with the exterior surface portion of the bump; and
a conductive via formed partially through the substrate with a surface of the conductive via opposite the encapsulant covered by the substrate.

14. The semiconductor device of claim 13 , further including an interconnect structure formed between the conductive via and bump.

15. The semiconductor device of claim 13 , wherein the bump is positioned over the conductive via.

16. The semiconductor device of claim 13 , wherein the bump is laterally offset from the conductive via.

17. The semiconductor device of claim 13 , further comprising disposing a second bump directly on the coplanar exterior surface of the first bump.

18. A semiconductor device, comprising:
a substrate;
an encapsulant deposited over the substrate;
a bump disposed in the encapsulant, wherein a surface of the encapsulant is coplanar with a surface of the bump; and
a conductive via formed partially through the substrate with the substrate disposed over the conductive via opposite the encapsulant.

19. The semiconductor device of claim 18 , wherein the substrate includes a semiconductor die.

20. The semiconductor device of claim 18 , further including a conductive layer formed between the conductive via and bump.

21. The semiconductor device of claim 18 , wherein the bump is positioned over the conductive via.

22. The semiconductor device of claim 18 , wherein the bump is laterally offset from the conductive via.

23. The semiconductor device of claim 18 , further comprising disposing a second bump directly on the coplanar surface of the first bump.

Assignees

• Stats Chippac Ltd
• Stats Chippac Pte Ltd

Inventors

• Marimuthu Pandi C
• Huang Shuangwu
• Suthiwongsunthorn Nathapong

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/655

  Fan-out layouts · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W72/50

  Bond wires · CPC title