Storage module and method for improved error correction by detection of grown bad bit lines

Patent metadata

Field	Value
Publication number	US-9436549-B2
Application number	US-201414502738-A
Country	US
Kind code	B2
Filing date	Sep 30, 2014
Priority date	Jul 31, 2014
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

In one embodiment, a storage module comprises a controller and a memory having a plurality of bit lines. The controller detects an uncorrectable error in a code word read from the memory, determines location(s) of grown bad bit line(s) that contributed to the error in the code word being uncorrectable, and uses the determined location(s) of the grown bad bit line(s) to attempt to correct the error in the code word.

First claim

What is claimed is:

1. A storage module comprising:
a memory having a plurality of bit lines; and
a controller in communication with the memory, wherein the storage controller is configured to:
detect an uncorrectable error in a code word read from the memory;
determine at least one location of at least one grown bad bit line that contributed to the error in the code word being uncorrectable; and
use the determined at least one location of the at least one grown bad bit line to attempt to correct the error in the code word.

2. The storage module of claim 1 , wherein the controller is configured to determine the at least one location of the at least one grown bad bit line by:
reading a plurality of additional code words that share the same bit lines as the code word that has the uncorrectable error; and
generating a histogram of error frequency of each of the bit lines.

3. The storage module of claim 2 , wherein the controller is further configured to:
apply a high-pass filter to the histogram to identify the at least one location of the at least one grown bad bit line.

4. The storage module of claim 2 , wherein the histogram also indicates an originally-stored value of a bit that was in error.

5. The storage module of claim 1 , wherein the controller implements an ECC engine using low-density parity-check (LDPC) code, and wherein the controller is configured modify a log likelihood ratio (LLR) of the ECC engine for the determined at least one location of the at least one grown bad bit line before attempting to correct the error.

6. The storage module of claim 1 , wherein the controller implements an ECC engine using BCH code, and wherein the controller is configured to flip at least one bit in the respective determined at least one location of the at least one grown bad bit line before attempting to correct the error.

7. The storage module of claim 1 , wherein the controller is configured to store the at least one location of the at least one grown bad bit line for later use in attempting to correct errors in additional code words later read from the at least one grown bad bit line.

8. The storage module of claim 1 , wherein the memory is a three-dimensional memory.

9. The storage module of claim 1 , wherein the storage module is embedded in a host.

10. The storage module of claim 1 , wherein the storage module is removably connected to a host.

11. A method for improved error correction by detection of at least one grown bad bit line, the method comprising:
performing the following in a storage module comprising a memory having a plurality of bit lines:
detecting an uncorrectable error in a code word read from the memory;
determining at least one location of at least one grown bad bit line that contributed to the error in the code word being uncorrectable; and
using the determined at least one location of the at least one grown bad bit line to attempt to correct the error in the code word.

12. The method of claim 11 , wherein the at least one location of the at least one grown bad bit line are determined by:
reading a plurality of additional code words that share the same bit lines as the code word that has the uncorrectable error; and
generating a histogram of error frequency of each of the bit lines.

13. The method of claim 12 further comprising:
applying a high-pass filter to the histogram to identify the at least one location of the at least one grown bad bit line.

14. The method of claim 12 , wherein the histogram also indicates an originally-stored value of a bit that was in error.

15. The method of claim 11 , wherein the storage module implements an ECC engine using low-density parity-check (LDPC) code, and wherein the method further comprises modifying a log likelihood ratio (LLR) of the ECC engine for the determined at least one location of the at least one grown bad bit line before attempting to correct the uncorrectable error.

16. The method of claim 11 , wherein the storage module implements an ECC engine using BCH code, and wherein the method further comprises flipping at least one bit in the determined at least one location of the at least one grown bad bit line before attempting to correct the uncorrectable error.

17. The method of claim 11 , wherein the method further comprises storing the at least one location of the at least one grown bad bit line for later use in attempting to correct errors in additional code words later read from the at least one grown bad bit line.

18. The method of claim 11 , wherein the memory is a three-dimensional memory.

19. The method of claim 11 , wherein the storage module is embedded in a host.

20. The method of claim 11 , wherein the storage module is removably connected to a host.

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Tuers Daniel E
• Manohar Abjiheet

Classifications

• H03M13/1111

  Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms · CPC title

• H03M13/6325

  Error control coding in combination with demodulation · CPC title

• H03M13/451

  using a set of candidate code words, e.g. ordered statistics decoding [OSD] · CPC title

• H03M13/152

  Bose-Chaudhuri-Hocquenghem [BCH] codes · CPC title

• H03M13/1102 Primary

  Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes · CPC title