Method, apparatus and instructions for parallel data conversions

Patent metadata

Field	Value
Publication number	US-9436433-B2
Application number	US-201514700736-A
Country	US
Kind code	B2
Filing date	Apr 30, 2015
Priority date	Sep 8, 2003
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits. The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

First claim

What is claimed is:

1. A reduced instruction set computer (RISC) processor comprising:
a register file, within the RISC processor, including a first packed data register and a second packed data register;
register rename logic within the RISC processor;
a decoder, within the RISC processor, to decode instructions, the instructions to include a first instruction;
schedule logic, within the RISC processor, to queue operations that correspond to the instructions for execution; and
execution logic, within the RISC processor, coupled to the decoder, the register rename logic, and the schedule logic, the execution logic to perform out-of-order execution of at least some of the instructions;
wherein, responsive to a decode of the first instruction by the decoder, the execution logic is to convert a first plurality of packed signed data elements to be stored in the first packed data register to a second plurality of packed unsigned data elements in the second packed data register, one or more of the second plurality of packed unsigned data elements to be saturated;
the first plurality of packed signed data elements to include floating point data elements and the second plurality of packed unsigned data elements to include integer data elements;
at least one of the packed signed data elements to have a first number of bits, at least one of the packed unsigned data elements to have a second number of bits, wherein the second number of bits is one half the first number of bits.

2. The processor of claim 1 , wherein the first number of bits is 64 and the second number of bits is 32.

3. The processor of claim 1 , wherein the one or more of the second plurality of packed unsigned data elements is to be saturated if a condition is satisfied.

Assignees

• Intel Corp

Inventors

• Ramanujam Gopalan

Classifications

• G06F9/30109

  having multiple operands in a single register · CPC title

• G06F15/82

  data or demand driven · CPC title

• G06F9/30014 Primary

  with variable precision · CPC title

• G06F9/30032

  Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE · CPC title

• G06F9/30145

  Instruction analysis, e.g. decoding, instruction word fields · CPC title