Method, apparatus and instructions for parallel data conversions

Patent metadata

Field	Value
Publication number	US-9032004-B2
Application number	US-201213682993-A
Country	US
Kind code	B2
Filing date	Nov 21, 2012
Priority date	Sep 8, 2003
Publication date	May 12, 2015
Grant date	May 12, 2015

Abstract

Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

First claim

What is claimed is:

1. A system comprising:
a processor comprising
a register file including a first packed data register and a second packed data register,
a decoder to decode a first instruction,
scheduling logic to allocate resources and queue operations corresponding to the first instruction for execution, and
execution logic coupled to the decoder and the scheduling logic,
wherein, responsive to the decoder decoding the first instruction, the execution logic is to convert a plurality of first packed signed data elements to a plurality of unsigned results,
wherein the plurality of first packed signed data elements from the first packed data register is converted to the plurality of unsigned results, the unsigned results are saturated and stored in the second packed data register, and each of the first packed signed data elements has a first number of bits, each of the unsigned results has a second number of bits, and the second number of bits is one half the first number of bits;
a memory controller coupled to the processor, wherein the memory controller is integral with the processor;
a communication interface to a wireless network, the communication interface coupled to the processor; and
a graphics interface to a display, the graphics interface coupled to the processor.

2. The system of claim 1 , wherein the first number of bits is 32 and the second number of bits is 16.

3. The system of claim 1 , wherein the first number of bits is 64 and the second number of bits is 32.

4. The system of claim 1 , wherein the processor further comprises register renaming logic to associate physical registers with architectural registers.

5. A system comprising:
a processor comprising
a register file including a first packed data register and a second packed data register,
a decoder to decode a first instruction,
scheduling logic to allocate resources and queue operations corresponding to the first instruction for execution, and
execution logic coupled to the decoder and the scheduling logic,
wherein, responsive to the decoder decoding the first instruction, the execution logic is to convert a plurality of first packed integer data elements to a plurality of integer results,
wherein the plurality of first packed integer data elements from the first packed data register is converted to the plurality of integer results, the integer results are saturated and stored in the second packed data register, and each of the first packed integer data elements has a first number of bits, each of the integer results has a second number of bits, and the second number of bits is one half the first number of bits;
a memory controller coupled to the processor, wherein the memory controller is integral with the processor;
a communication interface to a wireless network, the communication interface coupled to the processor; and
a graphics interface to a display, the graphics interface coupled to the processor.

6. The system of claim 5 , wherein the first number of bits is 32 and the second number of bits is 16.

7. The system of claim 5 , wherein the first number of bits is 64 and the second number of bits is 32.

8. The system of claim 5 , wherein the processor further comprises register renaming logic to associate physical registers with architectural registers.

Assignees

• Intel Corp

Inventors

• Ramanujam Gopalan

Classifications

• G06F15/82

  data or demand driven · CPC title

• G06F7/48

  using non-contact-making devices, e.g. tube, solid state device; using unspecified devices · CPC title

• G06F9/30014 Primary

  with variable precision · CPC title

• G06F9/3016

  Decoding the operand specifier, e.g. specifier format · CPC title

• G06F9/30109

  having multiple operands in a single register · CPC title