Method, apparatus and instructions for parallel data conversions

Patent metadata

Field	Value
Publication number	US-9032003-B2
Application number	US-201213625085-A
Country	US
Kind code	B2
Filing date	Sep 24, 2012
Priority date	Sep 8, 2003
Publication date	May 12, 2015
Grant date	May 12, 2015

Abstract

Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

First claim

What is claimed is:

1. A processor comprising:
a register file including a first packed data register and a second packed data register;
a decoder to decode a first instruction;
scheduling logic to allocate resources and queue operations corresponding to the first instruction for execution; and
execution logic coupled to the decoder and the scheduling logic;
wherein, responsive to the decoder decoding the first instruction, the execution logic is to convert a plurality of…

Assignees

• Intel Corp

Inventors

• Ramanujam Gopalan

Classifications

• G06F9/30014 Primary

  Physics · mapped topic

• G06F9/3016

  Physics · mapped topic

• G06F9/384 Primary

  Physics · mapped topic

• G06F9/30025

  Physics · mapped topic

• G06F9/30109

  Physics · mapped topic