Methods of manufacturing FINFET semiconductor devices using sacrificial gate patterns and selective oxidization of a fin

Patent metadata

Field	Value
Publication number	US-9431522-B2
Application number	US-201615003288-A
Country	US
Kind code	B2
Filing date	Jan 21, 2016
Priority date	May 10, 2013
Publication date	Aug 30, 2016
Grant date	Aug 30, 2016

Abstract

A method of manufacturing a semiconductor device includes patterning a substrate to form an active fin, forming a sacrificial gate pattern crossing over the active fin on the substrate, forming an interlayer insulating layer on the sacrificial gate pattern, removing the sacrificial gate pattern to form a gap region exposing the active fin in the interlayer insulating layer, and oxidizing a portion of the active fin exposed by the gap region to form an insulation pattern between the active fin and the substrate.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
patterning a semiconductor substrate to form an active pattern;
forming oxidation reducing spacers on upper sidewalls of the active pattern;
forming device isolation patterns spaced apart from bottom surfaces of the oxidation reducing spacers, the device isolation patterns exposing portions of lower sidewalls of the active pattern;
forming a dummy gate pattern crossing over the active pattern and the oxidation reducing spacers, the dummy gate pattern being in direct contact with the active pattern between the device isolation pattern and the oxidation reducing spacers;
forming protecting spacers on both sidewalls of the dummy gate pattern, the protecting spacers comprising a material having an etch selectivity with respect to the oxidation reducing spacers;
removing the dummy gate pattern to form a gate region exposing lower sidewalls of the active pattern between the protecting spacers;
oxidizing the lower sidewalls of the active pattern exposed by the gate region to form a local insulation pattern in the active pattern; and
forming a gate electrode in the gate region.

2. The method of claim 1 , wherein patterning the semiconductor substrate to form the active pattern comprises:
forming a mask pattern defining the active pattern on the semiconductor substrate;
etching the semiconductor substrate using the mask pattern as an etch mask, thereby forming trenches; and
forming device isolation layers exposing upper sidewalls of the active pattern in the trenches,
wherein the oxidation reducing spacers are formed on the device isolation layers.

3. The method of claim 2 , further comprising:
recessing top surfaces of the device isolation layers to form device isolation patterns exposing lower sidewalls of the active pattern after forming the oxidation reducing spacers.

4. The method of claim 1 , wherein the gate electrode is in direct contact with a sidewall of the local insulation pattern.

5. The method of claim 4 , further comprising:
forming device isolation patterns spaced apart from bottom surfaces of the oxidation reducing spacers before forming the dummy gate pattern, the device isolation patterns exposing portions of the lower sidewalls of the active pattern.

6. The method of claim 5 , wherein the dummy gate pattern is in direct contact with the active pattern between the device isolation pattern and the oxidation reducing spacer.

7. The method of claim 4 , further comprising:
forming sidewall spacers on sidewalls of the protecting spacers before the gate region is formed,
wherein the sidewall spacers comprise a different insulating material from the protecting spacers.

8. The method of claim 1 , wherein forming the gate electrode comprises:
removing the oxidation reducing spacers to expose an upper portion of the active pattern; and
forming a conductive layer in the gate region exposing the upper portion of the active pattern, the conductive layer directly contacting the protecting spacers.

9. The method of claim 1 , wherein the active pattern includes a channel region under the dummy gate pattern and source/drain regions at both sides of the channel region, the method further comprising:
forming an epitaxial layer at the source/drain regions of the active pattern before the gate region is formed.

10. A method of manufacturing a semiconductor device, the method comprising:
patterning a semiconductor substrate to form an active pattern;
forming oxidation reducing spacers on upper sidewalls of the active pattern;
forming a dummy gate pattern crossing over the active pattern and the oxidation reducing spacers;
forming protecting spacers on both sidewalls of the dummy gate pattern, the protecting spacers comprising a material having an etch selectivity with respect to the oxidation reducing spacers;
forming sidewall spacers on sidewalls of the protecting spacers, the sidewall spacers comprising a different insulating material from the protecting spacers;
forming an interlayer insulating layer on the semiconductor substrate to cover the sidewall spacers and to expose a top surface of the dummy gate pattern;
removing the dummy gate pattern to form a gate region exposing lower sidewalls of the active pattern between the protecting spacers;
oxidizing the lower sidewalls of the active pattern exposed by the gate region to form a local insulation pattern in the active pattern; and
forming a gate electrode in the gate region.

11. The method of claim 10 , further comprising:
forming device isolation patterns spaced apart from bottom surfaces of the oxidation reducing spacers before forming the dummy gate pattern, the device isolation patterns exposing portions of the lower sidewalls of the active pattern.

12. The method of claim 11 , wherein the dummy gate pattern is in direct contact with the active pattern between the device isolation pattern and the oxidation reducing spacer.

13. The method of claim 11 , wherein each of the protecting spacers includes a first portion on the sidewall of the dummy gate pattern and a second portion on the device isolation pattern, and
wherein each of the sidewall spacers is spaced apart from the device isolation pattern with the second portion interposed therebetween.

14. The method of claim 10 , wherein the gate electrode is in direct contact with a sidewall of the local insulation pattern.

15. A method of manufacturing a semiconductor device, the method comprising:
patterning a semiconductor substrate to form an active pattern;
forming oxidation reducing spacers on upper sidewalls of the active pattern;
forming a dummy gate pattern crossing over the active pattern and the oxidation reducing spacers;
forming protecting spacers on both sidewalls of the dummy gate pattern, the protecting spacers comprising a material having an etch selectivity with respect to the oxidation reducing spacers;
removing the dummy gate pattern to form a gate region exposing lower sidewalls of the active pattern between the protecting spacers;
oxidizing the lower sidewalls of the active pattern exposed by the gate region to form a local insulation pattern in the active pattern, a first height of the local insulation pattern under the oxidation reducing spacer being greater than a second height of the local insulation layer under the active pattern between the protecting spacers; and
forming a gate electrode in the gate region.

16. The method of claim 15 , wherein the local insulation pattern has an uneven top surface and an uneven bottom surface.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Sungmin
• Suk Sung-Dae
• Park Jaehoo
• Cha Dongho
• Ha Daewon

Classifications

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10P14/6306

  of the semiconductor materials · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D30/024 Primary

  of fin field-effect transistors [FinFET] · CPC title