Hybrid transformer structure on semiconductor devices

Patent metadata

Field	Value
Publication number	US-9431473-B2
Application number	US-201213684103-A
Country	US
Kind code	B2
Filing date	Nov 21, 2012
Priority date	Nov 21, 2012
Publication date	Aug 30, 2016
Grant date	Aug 30, 2016

Abstract

Several novel features pertain to a hybrid transformer formed within a semiconductor die having multiple layers. The hybrid transformer includes a first set of windings positioned on a first layer of the die. The first layer is positioned above a substrate of the die. The first set of windings includes a first port and a second port. The first set of windings is arranged to operate as a first inductor. The hybrid transformer includes a second set of windings positioned on a second layer of the die. The second layer is positioned above the substrate. The second set of windings includes a third port, a fourth port and a fifth port. The second set of windings is arranged to operate as a second inductor and a third inductor. The first set of windings and the second set of windings are arranged to operate as a vertical coupling hybrid transformer.

First claim

What is claimed is:

1. A hybrid transformer formed within a semiconductor die having multiple layers, the hybrid transformer comprising:
a first set of windings positioned on at least a first layer of the semiconductor die, the first layer positioned above a substrate of the semiconductor die, the first set of windings includes a first port and a second port, the first set of windings arranged to operate as a first inductor; and
a second set of windings positioned on at least a second layer of the semiconductor die, the second layer positioned above the substrate, the second set of windings includes a third port, a fourth port and a fifth port, the second set of windings arranged to operate as a second inductor and a third inductor, wherein the semiconductor die includes a third layer and a fourth layer, the first set of windings being positioned on the first layer and on the third layer, the second set of windings being positioned on the second layer and on the fourth layer, and wherein the first set of windings and the second set of windings are arranged to operate as a vertical coupling hybrid transformer.

2. The hybrid transformer of claim 1 , wherein the first set of windings and the second set of windings arranged to operate as the vertical coupling hybrid transformer are configured to transfer energy between the first set of windings and the second set of windings, and wherein a majority of a total energy that is transferred between the first set of windings and the second set of windings occurs between windings on different layers of the semiconductor die.

3. The hybrid transformer of claim 1 , wherein the first set of windings and the second set of windings arranged to operate as the vertical coupling hybrid transformer are configured to transfer energy between the first set of windings and the second set of windings, and wherein a substantial amount of a total energy that is transferred between the first set of windings and the second set of windings occurs between windings on different layers of the semiconductor die.

4. The hybrid transformer of claim 1 . wherein the substrate is an insulative radio frequency (RF) substrate.

5. The hybrid transformer of claim 1 , wherein the substrate is a glass substrate.

6. The hybrid transformer of claim 1 , wherein the semiconductor die includes a dielectric layer located between the first set of windings and the second set of windings.

7. The hybrid transformer of claim 6 , wherein the dielectric layer comprises a low k dielectric, a low-loss dielectric, or a combination thereof.

8. The hybrid transformer of claim 6 , wherein the dielectric layer comprises a polyimide material, an acrylic material, a polybenzoxazole (PBO) material, a benzocyclobutene (BCB) material, or a combination thereof.

9. The hybrid transformer of claim 1 , wherein the second layer is above the first layer.

10. The hybrid transformer of claim 1 , wherein the first layer is above the second layer.

11. The hybrid transformer of claim 1 , wherein the first set of windings is interleaved with the second set of windings on the multiples layers of the semiconductor die.

12. The hybrid transformer of claim 11 , wherein a first portion of the first set of windings and a first portion of the second set of windings are positioned on the first layer, wherein a second portion of the first set of windings and a second portion of the second set of windings are positioned on the third layer, wherein a third portion of the first set of windings and a third portion of the second set of windings are positioned on the second layer, and wherein a fourth portion of the first set of windings and a fourth portion of the second set of windings are positioned on the fourth layer.

13. The hybrid transformer of claim 1 , wherein the first set of windings includes a first set of conductive traces.

14. The hybrid transformer of claim 13 , wherein the first set of windings includes a first set of interconnects.

15. The hybrid transformer of claim 1 , wherein the first set of windings is symmetrical to the second set of windings.

16. The hybrid transformer of claim 1 , wherein the second set of windings is positioned and aligned directly above the first set of windings.

17. The hybrid transformer of claim 1 , wherein the first set of windings and the second set of windings are coaxial.

18. The hybrid transformer of claim 1 , wherein the first set of windings has a first number of loops, and wherein the second set of windings has a second number of loops.

19. The hybrid transformer of claim 1 , wherein the hybrid transformer operates as a signal duplexer.

20. The hybrid transformer of claim 1 , wherein the first port is positioned on the first layer, the second port is positioned on the third layer, the third port is positioned on the second layer, the fourth port is positioned on the second layer or the fourth layer, and the fifth port is positioned on the fourth layer.

21. A method for manufacturing a hybrid transformer in a semiconductor die, the method comprising:
forming a first set of windings positioned on at least a first layer of the semiconductor die, the first layer positioned above a substrate of the die, the first set of windings includes a first port and a second port, the first set of windings arranged to operate as a first inductor; and
forming a second set of windings positioned on at least a second layer of the semiconductor die, the second layer positioned above the substrate, the second set of windings includes a third port, a fourth port and a fifth port, the second set of windings arranged to operate as a second inductor and a third inductor, wherein the semiconductor die includes a third layer and a fourth layer, the first set of windings being positioned on the first layer and on the third layer, the second set of windings being positioned on the second layer and on the fourth layer, and wherein the first set of windings and the second set of windings are arranged to operate as a vertical coupling hybrid transformer.

22. The method of claim 21 , wherein the first set of windings and the second set of windings arranged to operate as the vertical coupling hybrid transformer are configured to transfer energy between the first set of windings and the second set of windings, and wherein a majority of a total energy that is transferred between the first set of windings and the second set of windings occurs between windings on different layers of the semiconductor die.

23. The method of claim 21 , wherein the first set of windings and the second set of windings arranged to operate as the vertical coupling hybrid transformer are configured to transfer energy between the first set of windings and the second set of windings, and wherein a substantial amount of a total energy that is transferred between the first set of windings and the second set of windings occurs between windings on different layers of the semiconductor die.

24. The method of claim 21 , wherein the substrate is an insulative radio frequency (RF) substrate.

25. The method of claim 21 , wherein the substrate is a glass substrate.

26. The method of claim 21 , wherein a dielectric layer is positioned between the first set of windings and the second windings.

27. The method of claim 26 , wherein the dielectric layer comprises a low k dielectric, a low-loss dielectric, or a combination thereof.

28. The

Assignees

• Qualcomm Inc

Inventors

• Lo Chi Shun
• Lan Je-Hsiung
• Velez Mario Francisco
• Kim Jonghae

Classifications

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10W44/501

  Inductive arrangements (H10W44/20 takes precedence) · CPC title

• H10W20/497

  Inductive arrangements or effects of, or between, wiring layers · CPC title

• H10D1/20 Primary

  Inductors · CPC title

• H01L28/10 Primary

  Electricity · mapped topic