Tunnel junction fabrication

Patent metadata

Field	Value
Publication number	US-9425377-B2
Application number	US-201414257898-A
Country	US
Kind code	B2
Filing date	Apr 21, 2014
Priority date	Apr 19, 2013
Publication date	Aug 23, 2016
Grant date	Aug 23, 2016

Abstract

A method for fabricating a tunnel junction includes depositing a first electrode on a substrate, depositing a wetting layer having a thickness of less than 2 nm on the first electrode, using atomic layer deposition (ALD) to deposit an oxide layer on the wetting layer, and depositing a second electrode on the oxide layer. The wetting layer and the oxide layer form a tunnel barrier, and the second electrode includes a superconductor.

First claim

What is claimed is:

1. A method for fabricating a superconducting quantum computer bit, the method comprising:
depositing a first electrode on a substrate;
depositing a first layer of a superconducting material on one end of the first electrode and on the substrate;
depositing a second layer of the superconducting material on another end of the first electrode and on the substrate;
depositing a wetting layer having a thickness of less than 2 nm on the first electrode, the wetting layer contacting both the first layer and the second layer of the superconducting material;
using atomic layer deposition (ALD) to deposit an oxide layer on the wetting layer, the oxide layer contacting both the first layer and the second layer of the superconducting material; and
depositing a second electrode on the oxide layer, the second electrode contacting both the first layer and the second layer of the superconducting material,
wherein the superconducting quantum computer bit comprises a tunnel barrier formed by the wetting layer and the oxide layer,
the first electrode comprises a non-superconducting material;
the second electrode comprises a superconducting material, and
a temperature of the superconducting quantum computer bit decreases when a voltage is applied across the first and second electrodes.

2. The method of claim 1 , wherein the wetting layer comprises Al, and the wetting layer is oxidized during ALD of the oxide layer.

3. The method of claim 1 , further comprising sputter etching the first electrode before the wetting layer is deposited onto the first electrode.

4. The method claim 1 , wherein the first electrode comprises Au, and the tunnel junction is a normal-insulating-superconducting (NIS) tunnel junction.

5. The method of claim 1 , wherein the tunnel barrier having an area of not less than 2500 μm 2 and a resistance of not more than kΩ.

6. The method of claim 1 , wherein the oxide layer comprises Al 2 O 3 , and using ALD to deposit the oxide layer comprises subjecting the wetting layer to a plurality of deposition cycles, each of the deposition cycles comprising a pulse of trimethyl aluminum (TMA) and a pulse of H 2 O.

7. The method of claim 6 , wherein each of the deposition cycles deposit less than 2 Å of Al 2 O 3 .

8. A superconducting quantum computer bit, comprising:
a substrate having a surface;
a first electrode deposited on the surface of the substrate;
a wetting layer deposited on the first electrode, the wetting layer being less than 2 nm in thickness;
an oxide layer deposited on the wetting layer;
a second electrode deposited on the oxide layer;

wherein:
the first electrode is formed using a material selected from the group consisting of a non-oxidizing metal, a metal that forms an incomplete oxide, and a metal that forms a conductive oxide,
the quantum computer bit is configured to operate at a temperature where the second electrode is superconducting,
thermal transfer occurs between the first electrode and the second electrode when a voltage is applied across the first and second electrodes;
a first layer of a superconducting material deposited on the substrate and a first end of the first electrode; and
a second layer of the superconducting material deposited on the substrate and another end of the first electrode,

wherein:
the oxide layer is in contact with the first and second layers of the superconducting material, and a temperature of the superconducting quantum computer bit is reduced when a voltage is applied between the first electrode and the second electrode.

9. The superconducting quantum computer bit of claim 8 , wherein the first electrode comprises Au.

10. The superconducting quantum computer bit of claim 8 , wherein the wetting layer is oxidized.

11. The superconducting quantum computer bit of claim 8 , wherein a point defect in the oxide layer is reduced compared to an oxide layer formed from thermal oxidation.

12. The superconducting quantum computer bit of claim 8 , wherein the first electrode and the second electrode are free of alloys.

13. The superconducting quantum computer bit of claim 8 , wherein the oxide layer has an area of not less than 2500 μm 2 .

Assignees

• Univ California

Inventors

• Moyerman Stephanie
• Keating Brian

Classifications

• H01L39/223

  Electricity · mapped topic

• H01L39/2493 Primary

  Electricity · mapped topic

• H01L39/228

  Electricity · mapped topic

• G06N99/002

  Physics · mapped topic

• G01K7/01 Primary

  using semiconducting elements having PN junctions (G01K7/02, G01K7/16, G01K7/30 take precedence) · CPC title