Modular array of vertically integrated superconducting qubit devices for scalable quantum computing
US-9524470-B1 · Dec 20, 2016 · US
US9425376B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9425376-B2 |
| Application number | US-201314138672-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 23, 2013 |
| Priority date | Dec 23, 2013 |
| Publication date | Aug 23, 2016 |
| Grant date | Aug 23, 2016 |
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In a “window-junction” formation process for Josephson junction fabrication, a spacer dielectric is formed over the first superconducting electrode layer, then an opening (the “window” is formed to expose the part of the electrode layer to be used for the junction. In an atomic layer deposition (ALD) chamber (or multi-chamber sealed system) equipped with direct or remote plasma capability, the exposed part of the electrode is sputter-etched with Ar, H 2 , or a combination to remove native oxides, etch residues, and other contaminants. Optionally, an O 2 or O 3 pre-clean may precede the sputter etch. When the electrode is clean, the tunnel barrier layer is deposited by ALD in-situ without further oxidant exposure.
Opening claim text (preview).
What is claimed is: 1. A method, comprising: forming a first superconducting layer over a substrate; forming a dielectric layer over the first superconducting layer; forming an opening in the dielectric layer to expose part of a surface of the first superconducting layer; sputter-etching the exposed part of the surface of the first superconducting layer; forming a non-superconducting layer by atomic layer deposition over the exposed part of the surface of the first superconducting layer; and forming a second superconducting layer over the non-superconducting layer; wherein the substrate is not subjected to a vacuum break between the sputter-etching and the forming of the non-superconducting layer. 2. The method of claim 1 , wherein the sputter-etching comprises at least one of argon or hydrogen. 3. The method of claim 1 , further comprising cleaning the exposed part of the surface of the first superconducting layer with an oxidant before the sputter-etching. 4. The method of claim 3 , wherein the oxidant comprises one of oxygen or ozone. 5. The method of claim 1 , wherein the substrate remains in a single process chamber throughout the sputter-etching and the forming of the non-superconducting layer. 6. The method of claim 1 , wherein the sputter-etching is performed in a first process chamber and the forming of the non-superconducting layer is performed in a second process chamber, wherein the first process chamber and the second process chamber share a controlled environment. 7. The method of claim 1 , wherein the first superconducting layer or the second superconducting layer comprises at least one of aluminum, niobium, tantalum, titanium, their nitrides, their alloys, a superconducting ceramic, or an organic superconductor. 8. The method of claim 1 , wherein a thickness of the first superconducting layer or the second superconducting layer is between about 50 nm and 200 nm. 9. The method of claim 1 , wherein an element present in the first superconducting layer is present in the second superconducting layer. 10. The method of claim 1 , wherein an element present in the first superconducting layer is present in the non-superconducting layer. 11. The method of claim 1 , wherein the dielectric layer comprises silicon oxide. 12. The method of claim 1 , wherein a width of the opening is between about 10 nm and 1000 nm. 13. The method of claim 1 , wherein the non-superconducting layer comprises an oxide. 14. The method of claim 1 , wherein the non-superconducting layer comprises one of silicon oxide, aluminum oxide, germanium oxide, hafnium oxide, niobium oxide, tantalum oxide, titanium oxide, zirconium oxide, or a combination thereof. 15. The method of claim 1 , wherein the non-superconducting layer comprises a non-superconducting metal. 16. The method of claim 1 , wherein the non-superconducting layer comprises copper, silver, or gold. 17. The method of claim 1 , wherein a thickness of the non-superconducting layer is between about 0.5 nm and 3 nm. 18. The method of claim 1 , further comprising patterning at least one of the first superconducting layer, the non-superconducting layer, or the second superconducting layer. 19. The method of claim 1 , further comprising plasma-treating, UV-irradiating, or annealing the non-superconducting layer. 20. The method of claim 1 , wherein the first superconducting layer and the second superconducting layer are operable as electrodes of a Josephson junction; and wherein the non-superconducting layer is operable as the tunnel barrier of a Josephson junction.
Electricity · mapped topic
of Josephson-effect devices · CPC title
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