Vertical tunnel field effect transistor

Patent metadata

Field	Value
Publication number	US-9425296-B2
Application number	US-201314021795-A
Country	US
Kind code	B2
Filing date	Sep 9, 2013
Priority date	Sep 9, 2013
Publication date	Aug 23, 2016
Grant date	Aug 23, 2016

Abstract

A tunnel field transistor (TFET) device includes a fin structure that protrudes from a substrate surface. The fin structure includes a base portion proximate to the substrate surface, a top portion, and a first pair of sidewalls extending from the base portion to the top portion. The first pair of sidewalls has a length corresponding to a length of the fin structure. The fin structure also includes a first doped region having a first dopant concentration at the base portion of the fin structure. The fin structure also includes a second doped region having a second dopant concentration at the top portion of the fin structure. The TFET device further includes a gate including a first conductive structure neighboring a first sidewall of the first pair of sidewalls. A dielectric layer electrically isolates the first conductive structure from the first sidewall.

First claim

What is claimed is:

1. A tunnel field effect transistor (TFET) device comprising:
a fin structure comprising:
a base portion having a portion disposed in a recess of a substrate and protruding through a plane of a surface of the substrate;
a top portion;
a pair of sidewalls extending from a part of the base portion to the top portion;
a first doped region having a first dopant concentration at the base portion; and
a second doped region having a second dopant concentration at the top portion; and

a gate comprising a first conductive structure neighboring a first sidewall of the pair of sidewalls; and
a dielectric layer that electrically isolates the first conductive structure from the first sidewall.

2. The TFET device of claim 1 , wherein the gate further comprises a second conductive structure neighboring a second sidewall of the pair of sidewalls, wherein the dielectric layer electrically isolates the second conductive structure from the second sidewall.

3. The TFET device of claim 2 , wherein the gate further comprises a third conductive structure neighboring the top portion, wherein the dielectric layer electrically isolates the third conductive structure from the top portion, and wherein the third conductive structure is coupled to the first conductive structure and to the second conductive structure.

4. The TFET device of claim 1 , wherein the fin structure further comprises a central portion between the base portion and the top portion.

5. The TFET device of claim 1 , wherein the base portion, the top portion, and a central portion between the base portion and the top portion are comprised of a first type of material.

6. The TFET device of claim 1 , wherein at least one of the base portion, the top portion, and a central portion between the base portion and the top portion comprises silicon.

7. The TFET device of claim 1 , wherein:
the top portion comprises an upper surface that is parallel to the surface of the substrate and is adjacent to another conductive structure of the gate, and
a central portion between the base portion and the top portion corresponds to a channel region of the fin structure.

8. The TFET device of claim 1 , wherein:
a central portion between the base portion and the top portion corresponds to a channel region of the fin structure, and
a channel length corresponds to a height of the central portion.

9. The TFET device of claim 1 , wherein a saturation current is adjusted by changing a width of the gate.

10. The TFET device of claim 1 , wherein the base portion corresponds to a drain of the fin structure and the top portion corresponds to a source of the fin structure.

11. The TFET device of claim 10 , wherein the first dopant concentration includes an n-type concentration and the second dopant concentration includes a p-type concentration.

12. The TFET device of claim 10 , wherein the first dopant concentration includes a p-type concentration and the second dopant concentration includes an n-type concentration.

13. The TFET device of claim 1 , wherein the first doped region comprises a first material and the second doped region comprises a second material, and wherein the first material is different from the second material.

14. The TFET device of claim 1 , wherein the base portion corresponds to a source of the fin structure and the top portion corresponds to a drain of the fin structure.

15. The TFET device of claim 14 , wherein the first dopant concentration includes an n-type concentration and the second dopant concentration includes a p-type concentration.

16. The TFET device of claim 14 , wherein the first dopant concentration includes a p-type concentration and the second dopant concentration includes an n-type concentration.

17. The TFET device of claim 1 , integrated into at least one semiconductor die.

18. The TFET device of claim 1 , integrated into a device selected from the group consisting of a communications device, a personal digital assistant (PDA), a navigation device, a fixed location data unit, a set top box, a music player, a video player, an entertainment unit, and a computer.

19. An apparatus comprising:
means for providing charge carriers to a tunneling channel;
means for receiving the charge carriers from the tunneling channel, wherein one of the means for providing or the means for receiving is at a base portion of a fin structure and is adjacent to a substrate surface, the base portion having a portion disposed in a recess of a substrate and protruding through a plane of a surface of the substrate, and wherein the other of the means for providing or the means for receiving is at a top portion of the fin structure; and
means for biasing the tunneling channel to enable band-to-band tunneling at the tunneling channel.

20. The apparatus of claim 19 , wherein the means for providing includes a source of the fin structure.

21. The apparatus of claim 19 , wherein the means for receiving includes a drain of the fin structure.

22. The apparatus of claim 19 , further comprising a device selected from the group consisting of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer, into which the means for providing, the means for receiving, and the means for biasing are integrated.

Assignees

• Qualcomm Inc

Inventors

• Li Xia
• Cai Ming
• Yang Bin

Classifications

• H10D30/63

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10D12/211

  Gated diodes · CPC title

• H10D12/021 Primary

  of gated diodes, e.g. field-controlled diodes [FCD] · CPC title

• H10D48/383 Primary

  Quantum effect devices, e.g. of devices using quantum reflection, diffraction or interference effects · CPC title