Semiconductor device and method of forming B-stage conductive polymer over contact pads of semiconductor die in Fo-WLCSP

US9418941B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9418941-B2
Application numberUS-201213438713-A
CountryUS
Kind codeB2
Filing dateApr 3, 2012
Priority dateAug 10, 2010
Publication dateAug 16, 2016
Grant dateAug 16, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor wafer contains a plurality of semiconductor die with bumps formed over contact pads on an active surface of the semiconductor die. A b-stage conductive polymer is deposited over the contact pads on the semiconductor wafer. The semiconductor wafer is singulated to separate the die. An insulating layer is formed over a carrier with openings formed in the insulating layer. The die is mounted to the carrier with the conductive polymer disposed in the openings of the insulating layer. The conductive polymer is heated to a glass transition temperature to liquefy the conductive polymer to an electrically conductive state. An encapsulant is deposited over the die and insulating layer. The carrier is removed to expose the conductive polymer. An interconnect structure is formed over the die, encapsulant, and conductive polymer. The interconnect structure is electrically connected through the conductive polymer to the contact pads on the die.

First claim

Opening claim text (preview).

What is claimed: 1. A semiconductor device, comprising: a semiconductor die including contact pads formed on an active surface of the semiconductor die; a first insulating layer disposed in contact with the active surface of the semiconductor die; a conductive polymer disposed in openings formed in the first insulating layer and in physical contact with the contact pads of the semiconductor die; an encapsulant disposed over the semiconductor die and the first insulating layer; and an interconnect structure formed in physical contact with the first insulating layer and conductive polymer, the interconnect structure being electrically connected through the conductive polymer to the contact pads on the active surface of the semiconductor die. 2. The semiconductor device of claim 1 , wherein the conductive polymer is at a glass transition temperature and in an electrically conductive state. 3. The semiconductor device of claim 1 , wherein the conductive polymer includes b-stage material. 4. The semiconductor device of claim 1 , wherein the first insulating layer provides stress relief. 5. The semiconductor device of claim 1 , wherein the interconnect structure includes: a conductive layer formed over the semiconductor die; and a second insulating layer formed over the conductive layer, encapsulant, and semiconductor die. 6. A semiconductor device, comprising: a semiconductor die including a contact pad formed on an active surface of the semiconductor die; a conductive polymer formed over the active surface in contact with the contact pad on the semiconductor die; an insulating layer disposed in contact with the active surface of the semiconductor die and the conductive polymer; an encapsulant deposited over the semiconductor die; and an interconnect structure formed over the active surface of the semiconductor die and the encapsulant, wherein the interconnect structure directly contacts the insulating layer and conductive polymer. 7. The semiconductor device of claim 6 , wherein the interconnect structure is electrically connected through the conductive polymer to the semiconductor die. 8. The semiconductor device of claim 6 , wherein the conductive polymer is at a glass transition temperature and in an electrically conductive state. 9. The semiconductor device of claim 6 , wherein the conductive polymer includes b-stage material. 10. The semiconductor device of claim 6 , wherein the interconnect structure includes a conductive layer formed over the semiconductor die and encapsulant. 11. The semiconductor device of claim 6 , wherein a thickness of the conductive polymer is equal to a thickness of the first insulating layer. 12. A semiconductor device, comprising: a semiconductor die; an encapsulant disposed over the semiconductor die; an insulating layer contacting an active surface of the semiconductor die and the encapsulant; a redistribution layer (RDL) formed over the insulating layer; and a conductive polymer disposed between the RDL and the active surface of the semiconductor die, wherein the RDL contacts the insulating layer and conductive polymer. 13. The semiconductor device of claim 12 , further including an interconnect structure formed over the RDL. 14. The semiconductor device of claim 13 , wherein the interconnect structure is electrically connected through the RDL and conductive polymer to the semiconductor die. 15. The semiconductor device of claim 13 , wherein the interconnect structure includes a bump. 16. The semiconductor device of claim 12 , wherein the conductive polymer is at a glass transition temperature and in an electrically conductive state. 17. The semiconductor device of claim 12 , wherein the conductive polymer includes b-stage material. 18. The semiconductor device of claim 12 , wherein a thickness of the conductive polymer is equal to a thickness of the insulating layer. 19. A semiconductor device, comprising: a semiconductor die; a conductive polymer formed over an active surface of the semiconductor die; an encapsulant deposited over the semiconductor die; an insulating layer contacting the active surface of the semiconductor die and the encapsulant around the conductive polymer; and a redistribution layer (RDL) formed in contact with the insulating layer and conductive polymer. 20. The semiconductor device of claim 19 , further including an interconnect structure formed over the RDL and electrically connected through the conductive polymer to the semiconductor die. 21. The semiconductor device of claim 20 , wherein the interconnect structure includes a bump. 22. The semiconductor device of claim 19 , wherein the conductive polymer is at a glass transition temperature and in an electrically conductive state. 23. The semiconductor device of claim 19 , wherein the conductive polymer includes b-stage material. 24. The semiconductor device of claim 19 , wherein a thickness of the conductive polymer is equal to a thickness of the insulating layer.

Assignees

Inventors

Classifications

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • Encapsulations, e.g. protective coatings · CPC title

  • on encapsulations · CPC title

  • in gaseous form, e.g. by CVD or PVD · CPC title

  • by plating, e.g. electroless plating or electroplating · CPC title

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What does patent US9418941B2 cover?
A semiconductor wafer contains a plurality of semiconductor die with bumps formed over contact pads on an active surface of the semiconductor die. A b-stage conductive polymer is deposited over the contact pads on the semiconductor wafer. The semiconductor wafer is singulated to separate the die. An insulating layer is formed over a carrier with openings formed in the insulating layer. The die …
Who is the assignee on this patent?
Do Byung Tai, Pagaila Reza A, Stats Chippac Pte Ltd
What technology area does this patent fall under?
Primary CPC classification H10W70/614. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 16 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).