Semiconductor component having through-silicon vias and method of manufacture

Patent metadata

Field	Value
Publication number	US-9418923-B2
Application number	US-201314033862-A
Country	US
Kind code	B2
Filing date	Sep 23, 2013
Priority date	Apr 13, 2011
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

A semiconductor component includes a semiconductor substrate having an opening A first dielectric liner having a first compressive stress is disposed in the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner.

First claim

What is claimed:

1. A semiconductor component comprising:
a semiconductor substrate having an opening, wherein the opening has a top portion and a bottom portion;
a first dielectric liner disposed over an interior surface of the opening, the first dielectric liner having a thickness T 1 on the top portion and a thickness T 2 on the bottom portion, wherein R 1 is a ratio of T 1 to T 2 ;
a second dielectric liner disposed over the first dielectric liner, the second dielectric liner having a thickness T 3 on the top portion and a thickness T 4 on the bottom portion, wherein R 2 is a ratio of T 3 to T 4 , and R 1 is greater than R 2 ; and
a conductive material disposed over the second dielectric liner.

2. The semiconductor component of claim 1 , wherein R 1 ranges from about 5 to about 20.

3. The semiconductor component of claim 1 , wherein the semiconductor substrate has a thickness ranging from about 10 microns (μm) to about 200 μm.

4. The semiconductor component of claim 1 , wherein R 2 ranges from about 1 to about 5.

5. The semiconductor component of claim 1 , further comprising a third dielectric liner between the second dielectric liner and the conductive material, the third dielectric liner has a thickness T 5 on the top portion and a thickness T 6 on the bottom portion, wherein R 3 is a ratio of T 5 to T 6 , and R 3 is greater than R 2 .

6. The semiconductor component of claim 5 , wherein R 3 ranges from about 5 to about 20.

7. The semiconductor component of claim 5 , wherein an etching rate of the first dielectric liner in an HF solution is different from an etching rate of the second dielectric liner in the HF solution.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yu Chen-Hua
• Chang Cheng-Hung
• Liao Ebin
• Yu Chia-Lin
• Wang Hsiang-Yi
• Chang Chun Hua
• Huang Li-Hsien
• Kuo Darryl
• Wu Tsang-Jiuh
• Chiou Wen-Chih

Classifications

• H10W20/0265

  characterised by the sidewall insulation · CPC title

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P52/403

  of conductive or resistive materials · CPC title

• H10P52/402

  of semiconductor materials · CPC title