Method of three dimensional integrated circuit assembly

Patent metadata

Field	Value
Publication number	US-9418876-B2
Application number	US-201113224575-A
Country	US
Kind code	B2
Filing date	Sep 2, 2011
Priority date	Sep 2, 2011
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

A method of fabricating a three-dimensional integrated circuit comprises attaching a wafer to a carrier, mounting a plurality of semiconductor dies on top of the wafer to form a wafer stack. The method further comprises forming a molding compound layer on top of the wafer, attaching the wafer stack to a tape frame and dicing the wafer stack to separate the wafer stack into a plurality of individual packages.

First claim

What is claimed is:

1. A method comprising:
attaching a first side of a wafer to a carrier;
mounting a plurality of semiconductor dies on top of a second side of the wafer to form a wafer stack, the first side being opposite of the second side, wherein a height of a first semiconductor die is equal to a height of a second semiconductor die and the height of the first semiconductor die is greater than a height of a third semiconductor die, and wherein the first semiconductor die, the second semiconductor die and the third semiconductor die are directly attached to the second side of the wafer;
attaching top surfaces of the first semiconductor die and the second semiconductor die to a tape frame, wherein there is a gap between a top surface of the third semiconductor die and the tape frame; and
dicing the wafer stack to separate the wafer stack into a plurality of individual packages.

2. The method of claim 1 , further comprising:
forming a first underfill layer between the wafer and the carrier.

3. The method of claim 1 , further comprising:
forming a second underfill layer between the wafer and the plurality of semiconductor dies.

4. The method of claim 1 , further comprising:
de-bonding the wafer stack from the carrier.

5. The method of claim 1 , further comprising:
detaching each individual package from the tape frame; and
attaching the individual package on a substrate layer.

6. The method of claim 5 , further comprising:
detaching each individual package from the tape frame using a pick-and-place process.

7. The method of claim 1 , further comprising:
forming a plurality of first bumps on a first side of the wafer; and
forming a plurality of second bumps on a second side the wafer.

8. A method comprising:
attaching a first side of a wafer to a carrier;
mounting a plurality of semiconductor dies on top of a second side of the wafer to form a wafer stack, the first side being opposite of the second side, wherein a height of a first semiconductor die is equal to a height of a second semiconductor die and the height of the first semiconductor die is greater than a height of a third semiconductor die;
encapsulating the second side of the wafer stack with a molding compound layer;
before de-bonding the carrier from the wafer stack, attaching top surfaces of the semiconductor dies to a tape frame; and
sawing the wafer stack into a plurality of individual packages.

9. The method of claim 8 , further comprising:
embedding the plurality of semiconductor dies into the molding compound layer.

10. The method of claim 8 , further comprising:
forming a plurality of first bumps on a first side of the wafer;
forming a plurality of second bumps on a second side of the wafer; and
forming a redistribution layer on the second side of the wafer.

11. The method of claim 8 , further comprising:
forming a first underfill layer between the wafer and the carrier; and
forming a second underfill layer between the wafer and the plurality of semiconductor dies.

12. The method of claim 8 , further comprising:
detaching each individual package from the tape frame using a pick-and-place process; and
attaching the individual package on a substrate.

13. The method of claim 8 , further comprising:
forming a plurality of through-silicon vias in the wafer.

14. A method comprising:
attaching a first side of a wafer to a carrier;
mounting a first semiconductor die and a second semiconductor die on a second side of the wafer, the second side being opposite of the first side, the first semiconductor die being laterally adjacent the second semiconductor die;
forming a molding compound along sidewalls of the first semiconductor die and the second semiconductor die, a top surface of the molding compound being above a top surface of the second semiconductor die; and
attaching the top surface of the first semiconductor die and the top surface of the molding compound to a tape frame, the top surface of the first semiconductor die physically contacting the tape frame.

15. The method of claim 14 , further comprising dicing the wafer into a plurality of individual packages.

16. The method of claim 15 , further comprising:
detaching at least one individual package of the plurality of individual packages from the tape frame; and
mounting the at least one individual package on a substrate.

17. The method of claim 14 , further comprising de-bonding the wafer from the carrier.

18. The method of claim 14 , further comprising:
forming a plurality of first bumps on the first side of the wafer; and
forming a plurality of second bumps on the second side the wafer.

19. The method of claim 18 , further comprising:
forming a first underfill layer on the first side of the wafer, the first underfill layer encapsulating the plurality of first bumps; and
forming a second underfill layer on the second side of the wafer, the second underfill layer encapsulating the plurality of second bumps.

20. The method of claim 14 , further comprising forming a redistribution layer on the second side of the wafer.

21. The method of claim 14 , further comprising forming a plurality of through vias in the wafer.

Assignees

• Lin Jing-Cheng
• Wu Weng-Jin
• Lin Shih Ting
• Huang Cheng-Lin
• Lu Szu Wei
• Jeng Shin-Puu
• Yu Chen-Hua
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Jing-Cheng
• Wu Weng-Jin
• Lin Shih Ting
• Huang Cheng-Lin
• Lu Szu Wei
• Jeng Shin-Puu
• Yu Chen-Hua

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/072

  of bump connectors · CPC title