Techniques for forming interconnects in porous dielectric materials

Patent metadata

Field	Value
Publication number	US-9406615-B2
Application number	US-201314139970-A
Country	US
Kind code	B2
Filing date	Dec 24, 2013
Priority date	Dec 24, 2013
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

Techniques are disclosed for forming interconnects in porous dielectric materials. In accordance with some embodiments, the porosity of a host dielectric layer may be reduced temporarily by stuffing its pores with a sacrificial pore-stuffing material, such as titanium nitride (TiN), titanium dioxide (TiO 2 ), or other suitable sacrificial material having a high etch selectivity compared to the metallization and dielectric material of the interconnect. After interconnect formation within the stuffed dielectric layer, the sacrificial pore-stuffing material can be removed from the pores of the host dielectric. In some cases, removal and curing can be performed with minimal or otherwise negligible effect on the dielectric constant (κ-value), leakage performance, and/or time-dependent dielectric breakdown (TDDB) properties of the host dielectric layer. Some embodiments can be utilized, for example, in processes involving atomic layer deposition (ALD)-based and/or chemical vapor deposition (CVD)-based backend metallization of highly porous, ultra-low-κ (ULK) dielectric materials.

First claim

What is claimed is:

1. An integrated circuit comprising:
a porous insulator layer having a plurality of pores, wherein substantially all of the pores within the porous insulator layer contain at least a trace amount of refractory material, such that the trace amount is detectable but negligible with respect to dielectric constant of the porous insulator layer; and
a first interconnect formed within the porous insulator layer.

2. The integrated circuit of claim 1 , wherein the porous insulator layer comprises at least one of silicon dioxide (SiO 2 ), a carbon (C)-doped silicon oxide, a carbosiloxane, a carbosilane, a nitrogen (N)-doped variation of any thereof, and a combination of any one or more of the aforementioned.

3. The integrated circuit of claim 1 , wherein the porous insulator layer has a dielectric constant (κ-value) in the range of about 1.6-2.3.

4. The integrated circuit of claim 1 , wherein the porous insulator layer has a dielectric constant (κ-value) of less than or equal to about 1.6.

5. The integrated circuit of claim 1 , wherein the porous insulator layer has a dielectric constant (κ-value) in the range of about 2.3-2.7.

6. The integrated circuit of claim 1 , wherein the pores of the porous insulator layer have an average pore size in the range of about 1-30 nm.

7. The integrated circuit of claim 1 , wherein the refractory material comprises at least one of titanium nitride (TiN), titanium dioxide (TiO 2 ), silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), amorphous silicon (a-Si), tungsten (W), a metal oxide, a metal nitride, and a combination of any one or more thereof.

8. The integrated circuit of claim 1 , wherein the refractory material comprises titanium (Ti).

9. The integrated circuit of claim 1 , wherein the refractory material is compatible with processing temperatures in the range of about 300-500° C.

10. The integrated circuit of claim 1 , wherein the refractory material deposited within the pores of the porous dielectric layer provides that layer with electrical conductivity.

11. The integrated circuit of claim 1 further comprising at least one of a lower metallized layer and a logic device formed under the porous insulator layer.

12. A method of forming an integrated circuit, the method comprising:
forming a porous insulator layer over a lower circuit layer;
depositing a refractory material within pores of the porous insulator layer;
forming an interconnect structure within the porous insulator layer; and
removing at least some of the refractory material from the pores of the porous insulator layer.

13. The method of claim 12 , wherein the porous insulator layer comprises at least one of silicon dioxide (SiO 2 ), a carbon (C)-doped silicon oxide, a carbosiloxane, a carbosilane, a nitrogen (N)-doped variation of any thereof, and a combination of any one or more of the aforementioned.

14. The method of claim 12 , wherein the refractory material comprises at least one of titanium nitride (TiN), titanium dioxide (TiO 2 ), silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), amorphous silicon (a-Si), tungsten (W), a metal oxide, a metal nitride, and a combination of any one or more thereof.

15. The method of claim 12 , wherein depositing the refractory material within the pores of the porous insulator layer comprises using at least one of an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, and a spin-on deposition (SOD) process.

16. The method of claim 12 , wherein depositing the refractory material within the pores of the porous insulator layer comprises using a stop-flow, ultra-conformal deposition process.

17. The method of claim 12 , wherein removing at least some of the refractory material from the pores of the porous insulator layer comprises using a wet etch process.

18. The method of claim 12 further comprising:
curing the porous insulator layer.

19. The method of claim 18 , wherein curing the porous insulator layer utilizes exposure to at least one of a diffuse electron beam, ultraviolet (UV) photons, infrared (IR) photons, and a temperature in the range of about 200-450° C.

20. An integrated circuit formed by the method of claim 12 , wherein substantially all of the pores within the porous insulator layer contain at least a trace amount of the refractory material, such that the trace amount is detectable but negligible with respect to dielectric constant of the porous insulator layer.

21. An integrated circuit comprising:
a porous dielectric layer having a plurality of pores, wherein substantially all of the pores within the porous insulator layer contain at least a trace amount of titanium (Ti), titanium nitride (TiN), or titanium dioxide (TiO 2 ), such that the trace amount is detectable but negligible with respect to dielectric constant of the porous dielectric layer; and
an interconnect formed within the porous dielectric layer.

22. The integrated circuit of claim 21 , wherein the porous dielectric layer comprises at least one of silicon dioxide (SiO 2 ), a carbon (C)-doped silicon oxide, a carbosiloxane, a carbosilane, a nitrogen (N)-doped variation of any thereof, and a combination of any one or more of the aforementioned.

23. The integrated circuit of claim 21 , wherein the porous dielectric layer has a dielectric constant (κ-value) that is less than or equal to about 2.7.

24. The integrated circuit of claim 21 , wherein the interconnect comprises at least one of copper (Cu), cobalt (Co), molybdenum (Mo), rhodium (Rh), beryllium (Be), chromium (Cr), manganese (Mn), aluminum (Al), ruthenium (Ru), palladium (Pd), tungsten (W), nickel (Ni), cobalt tungsten phosphide (CoWP), cobalt tungsten boron (CoWB), copper germanium (CuGe), silicon (Si), and a combination of any one or more thereof.

25. The integrated circuit of claim 21 further comprising a barrier layer formed between the interconnect and the porous dielectric layer, wherein the barrier layer comprises at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), manganese (Mn), manganese nitride (MnN), molybdenum (Mo), molybdenum nitride (MoN), cobalt tungsten phosphide (CoWP), cobalt tungsten boron (CoWB), and a combination of any one or more thereof.

Assignees

• Intel Corp

Inventors

• Jezewski Christopher J
• Michalak David J
• Singh Kanwal Jit
• Myers Alan M

Classifications

• H10P14/665

  Porous materials · CPC title

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/4403

  based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title