Silicon single crystal wafer, manufacturing method thereof and method of detecting defects

Patent metadata

Field	Value
Publication number	US-9406528-B2
Application number	US-201314028063-A
Country	US
Kind code	B2
Filing date	Sep 16, 2013
Priority date	Jan 8, 2013
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

A silicon single crystal wafer is provided. The silicon single crystal wafer includes an IDP which is divided into an NiG region and an NIDP region, wherein the IDP region is a region where a Cu based defect is not detected, the NiG region is a region where an Ni based defect is detected and the NIPD region is a region where an Ni based defect is not detected.

First claim

What is claimed is:

1. A silicon single crystal wafer comprising a VDP region having both a Cu based defect and a Ni based defect, an IDP region that is divided into a NiG region and an NIDP region surrounding the NiG region, wherein the NiG region has the Ni based defect and does not have the Cu based defect, and the NIDP region does not have the Ni based defect and does not have the Cu based defect.

2. The silicon single crystal wafer according to claim 1 , wherein the Ni based defect is a metal precipitate that is formed by a combination of Ni material with an oxygen precipitate of the silicon single crystal wafer.

3. The silicon single crystal wafer according to claim 1 , wherein the NiG region is provided between the VDP region and the NIDP region.

4. The silicon single crystal wafer according to claim 1 , wherein a pulling speed of the NiG region is between a pulling speed of the VDP region and a pulling speed of the NIDP region.

5. The silicon single crystal wafer according to claim 1 , wherein a pulling speed of the NiG region is lower than a pulling speed of the VDP region and higher than a pulling speed of the NIDP region.

6. A silicon single crystal wafer, comprising:
a first region having a first pulling speed;
a second region having a second pulling speed, wherein the second pulling speed is higher than the first pulling speed; and
a third region having a third pulling speed, wherein the third pulling speed is higher than the second pulling speed,
wherein the second region has a Ni based defect but does not have a Cu based defect, and
wherein the third region has both the Ni based defect and the Cu based defect.

7. The silicon single crystal wafer according to claim 6 , wherein the first region does not have the Ni based defect and the Cu based defect.

8. The silicon single crystal wafer according to claim 6 , wherein the first region is an NIDP region, the second region is an NiG region, and the third region is a VDP region.

9. A silicon single crystal wafer comprising:
a VDP region having a Cu based defect and a Ni based defect;
an NIDP region surrounding the VDP region and not having both the Cu based defect and the Ni based defect; and
an NiG region provided between the VDP region and the NIDP region and surrounding the VDP region, wherein the NiG region does not have the Cu based defect but has the Ni based defect.

10. The silicon single crystal wafer according to claim 9 , wherein a pulling speed of the NiG region is between a pulling speed of the VDP region and a pulling speed of the NIDP region.

11. The silicon single crystal wafer according to claim 9 , wherein a pulling speed of the NiG region is lower than a pulling speed of the VDP region and higher than a pulling speed of the NIDP region.

Assignees

• Lg Siltron Inc

Inventors

• Sim Woo Young

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P36/20 Primary

  Intrinsic gettering, i.e. thermally inducing defects by using oxygen present in the silicon body · CPC title

• H10P14/3822

  Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing · CPC title

• H10P14/3458

  Monocrystalline · CPC title