Data storage device and operation method thereof

Patent metadata

Field	Value
Publication number	US-9406386-B2
Application number	US-201514797203-A
Country	US
Kind code	B2
Filing date	Jul 13, 2015
Priority date	Jul 29, 2014
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

A data storage device includes a nonvolatile memory having a plurality of first memory cells connected to a first word line and a plurality of second memory cells connected to a second word line. A memory controller divides first data to be programmed in the first memory cells into first and second data groups and divides second data to be programmed in the second memory cells into third and fourth data groups. The nonvolatile memory device performs a third program operation of the second data group and a fourth program operation of the fourth data group after sequentially performing a first program operation of the first data group and a second program operation of the third data group.

First claim

What is claimed is:

1. A data storage device comprising:
a nonvolatile memory comprising a plurality of first memory cells connected to a first word line and a plurality of second memory cells connected to a second word line; and
a memory controller dividing first data to be programmed in the first memory cells into first and second data groups and dividing second data to be programmed in the second memory cells into third and fourth data groups, wherein:
the nonvolatile memory sequentially performs a third program operation of the second data group and then a fourth program operation of the fourth data group after sequentially performing a first program operation of the first data group and then a second program operation of the third data group,
the first data group is programmed in first selection memory cells among the first memory cells and the second data group is programmed in second selection memory cells different from the first selection memory cells among the first memory cells, and
the third data group is programmed in third selection memory cells among the second memory cells and the fourth data group is programmed in fourth selection memory cells different from the third selection memory cells among the second memory cells.

2. The data storage device of claim 1 , wherein the memory controller provides the first and third data groups to the nonvolatile memory on the basis of the first and second program operations and provides the second and fourth data groups to the nonvolatile memory on the basis of the third and fourth program operations.

3. The data storage device of claim 1 , wherein a threshold voltage of the first selection memory cells is higher than a threshold voltage of the second selection memory cells and a threshold voltage of the third selection memory cells is higher than a threshold voltage of the fourth selection memory cells.

4. A nonvolatile memory device comprising:
a memory cell array comprising a plurality of first memory cells connected to a first word line and a plurality of second memory cells connected to a second word line; and
a page buffer circuit receiving one of first data to be programmed in the first memory cells and second data to be programmed in the second memory cells and dividing the received data into a first data group and a second data group, wherein:
in a first program operation, the page buffer circuit programs the first data group in the first memory cells of any one word line selected between the first and second word lines, and
in a second program operation, the page buffer circuit programs the second data group in the second memory cells different from the first memory cells of the selected word line.

5. The nonvolatile memory device of claim 4 , further comprises:
control logic providing a control signal to the page buffer circuit, wherein
the page buffer circuit programs any one data group between the first and second data groups in the memory cell array in response to the control signal.

6. The nonvolatile memory device of claim 5 , wherein:
the control logic receives first and second command signals from outside, and
the control logic provides a control signal of a first level to the page buffer circuit in response to the first command signal and provides a control signal of a second level to the page buffer circuit in response to the second command signal.

7. The nonvolatile memory device of claim 6 , wherein:
the page buffer circuit programs the first data group in the memory cell array in response to the control signal of the first level, and
the page buffer circuit programs the second data group in the memory cell array in response to the control signal of the second level.

8. The nonvolatile memory device of claim 4 , wherein the page buffer circuit comprises:
a first latch storing the received data;
a determination unit comparing division information previously set with bit information corresponding to each of the received data and determining a data group of each of the received data according to a comparison result; and
a second latch storing data group information of each of the data according to the determination result.

9. The nonvolatile memory device of claim 8 , wherein the number of bits being stored in the first latch is larger than the number of bits being stored in the second latch.

10. The nonvolatile memory device of claim 8 , wherein the division information previously set comprises at least one data pattern among data patterns being programmed in each of the first and second memory cells.

11. The nonvolatile memory device of claim 8 , wherein the determination unit determines data having a data pattern corresponding to the division information previously set among the received data as the first data group and determines data having a data pattern not corresponding to the division information previously set among the received data as the second data group.

12. The nonvolatile memory device of claim 11 , wherein the second latch provides a selection signal selecting data determined as the first data group among the received data to the first latch in response to a first level of a control signal.

13. The nonvolatile memory device of claim 11 , wherein the second latch provides a selection signal selecting data determined as the second data group among the received data to the first latch in response to a second level of a control signal.

14. The nonvolatile memory device of claim 8 , wherein a threshold voltage of memory cells being programmed in response to receiving the first data divided into the first data group is higher than a threshold voltage of memory cells being programmed in response to receiving the second data divided into the second data group.

15. The nonvolatile memory device of claim 8 , wherein the page buffer circuit further comprises a data buffer storing data received from the first latch.

16. The nonvolatile memory device of claim 15 , wherein in the second program operation, the data buffer provides the received data to the first latch.

17. The nonvolatile memory device of claim 4 , wherein the page buffer is reset between after the first program operation is performed and before the second program operation is performed.

18. An operation method of a data storage device comprising a nonvolatile memory having at least one memory block, the method comprising:
dividing first data to be programmed in a plurality of first memory cells connected to a first word line of the at least one memory block into first and second data groups;
dividing second data to be programmed in a plurality of second memory cells connected to a second word line of the at least one memory block into third and fourth data groups;
performing a first program operation of the first data group;
performing a second program operation of the third data group;
performing a third program operation of the second data group; and
performing a fourth program operation of the fourth data group, wherein:
the first data group is programmed in first selection memory cells among the first memory cells and the second data group is programmed in second selection memory cells different from the first selection memory cells among the first memory cells, and
the third data group is programmed in third selection memory cells among the second memory cells and the fourth data group is programmed in fourth selection memory cells different from the third selection memory cells among the second memory cells.

19. The operation method of a data storage device of

Assignees

• Yu Jae-Duk
• Kim Chul Bum
• Kang Dongku
• Samsung Electronics Co Ltd

Inventors

• Yu Jae-Duk
• Kim Chul Bum
• Kang Dongku

Classifications

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C2211/5648

  Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant · CPC title