Nonvolatile memory device and sub-block managing method thereof

Patent metadata

Field	Value
Publication number	US-9256530-B2
Application number	US-201514610512-A
Country	US
Kind code	B2
Filing date	Jan 30, 2015
Priority date	Aug 31, 2012
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

A nonvolatile memory device includes a memory block, a row decoder, a voltage generator and control logic. The memory block includes memory cells stacked in a direction intersecting a substrate, the memory block being divided into sub-blocks configured to be erased independently. The row decoder is configured to select the memory block by a sub-block unit. The voltage generator is configured to generate an erase word line voltage to be provided to a first word line of a selected sub-block of the sub-blocks and a cut-off voltage, higher than the erase word line voltage, to be provided to a second word line of the selected sub-block during an erase operation. The control logic is configured to control the row decoder and the voltage generator to perform an erase operation on the selected sub-block.

First claim

What is claimed is:

1. A method of managing a nonvolatile memory device to erase memory cells by sub-block unit, a sub-block being smaller than a physical block of the nonvolatile memory device, the physical block of the nonvolatile memory device comprises a three-dimensional memory array, the method comprising:
checking a status of an unselected sub-block being adjacent to a selected sub-block; and
adjusting a level of a first voltage based on the status of the unselected sub-block; and
performing an erase operation on the selected sub-block by providing at least one word line of the selected sub-block with the adjusted first voltage for blocking interference with the unselected sub-block.

2. The method of claim 1 , wherein the at least one word line supplied with the first voltage is adjacent to the unselected sub-block, and the first voltage being higher than an erase word line voltage provided to remaining word lines of the selected sub-block.

3. The method of claim 1 , wherein the status of the unselected sub-block comprises at least one among erase-inhibition efficiency, a variation in threshold voltage of memory cells, and a variation in bit error rate of the memory cells.

4. The method of claim 1 , wherein the adjusting a level of the first voltage comprises decreasing the level of the first voltage when the status of the unselected sub-block meets a reference.

5. The method of claim 4 , wherein if a threshold voltage of memory cells of the unselected sub-block is equal to or higher than the reference, the status of the unselected sub-block is determined to meet the reference.

6. The method of claim 1 , wherein the adjusting a level of the first voltage comprises increasing a level of the first voltage when the status of the unselected sub-block falls short of a reference.

7. The method of claim 6 , further comprising:
adjusting a number of bits stored in each of the memory cells connected to the at least one word line provided with the first voltage.

8. The method of claim 7 , wherein the number of bits stored in each of the memory cells decreases when the status of the unselected sub-block falls short of the reference.

9. The method of claim 1 , further comprising:
checking an erase status of the selected sub-block;
when the erase status and the status of the unselected sub-block do not reach a reference, respectively, increasing a level of the first voltage; and
decreasing the number of bits stored in each of memory cells connected to the at least one word line provided with the first voltage.

10. The method of claim 1 , wherein the first voltage corresponds to a cut-off voltage for cutting off an interference of a word line voltage, applied to the selected sub-block during the erase operation, on the unselected sub-block.

11. A storage device, comprising:
a nonvolatile memory device configured to erase a memory block in sub-block unit, and being configured to provide a first voltage to a word line among a plurality of word lines in a selected sub-block adjacent to an unselected sub-block, and to provide an inner voltage to word lines in the selected sub-block that are not adjacent to the unselected sub-block during an erase operation; and
a memory controller configured to control the nonvolatile memory device to adjust a level of the first voltage to be applied to the word line in the selected sub-block during the erase operation of the selected sub-block based on a status of the unselected sub-block,
wherein the nonvolatile memory device comprises a three-dimensional memory cell array including a charge trap layer.

12. The storage device of claim 11 , wherein the nonvolatile memory device comprises a voltage generator configured to provide the first voltage being higher than the inner voltage to a first word line among the plurality of word lines in the selected sub-block.

13. The storage device of claim 12 , wherein the voltage generator is further configured to provide a second voltage, lower than the first voltage and higher than the inner voltage, to a second word line of the plurality of word lines in the selected sub-block adjacent to the first word line during the erase operation.

14. The storage device of claim 11 , wherein the memory controller comprises an erase status detector configured to check the status of the unselected sub-block.

15. The storage device of claim 14 , wherein when the status of the unselected sub-block does not reach a reference, the memory controller increases the level of the first voltage to be provided during a subsequent erase operation of the selected sub-block.

16. The storage device of claim 14 , wherein when the status of the unselected sub-block meets a reference, the memory controller decreases the level of the first voltage to be provided during a subsequent erase operation of the selected sub-block.

17. The storage device of claim 14 , wherein when an erase status of the selected sub-block and the status of the unselected sub-block do not reach a reference, respectively, the memory controller controls the nonvolatile memory device to increase the level of the first voltage, and the memory controller controls the nonvolatile memory device to decrease the number of bits stored in each of memory cells connected to at least one word line provided with the first voltage.

18. The storage device of claim 11 , wherein the selected sub-block and the unselected sub-block are included in a same physical block.

19. A three dimensional nonvolatile memory device comprising:
a memory block being divided into a plurality of sub-blocks configured to be erased independently;
a row decoder configured to select the memory block by a sub-block unit;
a voltage generator configured to generate an erase voltage to be provided to a first word line of a selected sub-block among the plurality of sub-blocks and a first voltage to be provided to a second word line of the selected sub-block during an erase operation; and
a control logic configured to control the row decoder and the voltage generator to perform an erase operation on the selected sub-block,
wherein the voltage generator is configured to adjust a level of the first voltage based on a status of the unselected sub-block, and
wherein the first voltage is higher than the erase voltage.

20. The three dimensional nonvolatile memory device of claim 19 , when a threshold voltage of at least one memory cell of the unselected sub-block is lower than a reference value owing to a previous erase operation on the selected sub-block, and the level of the first voltage is increased during a subsequent erase operation of the selected sub-block.

Assignees

• Oh Eun Chu
• Kong Junjin
• Samsung Electronics Co Ltd

Inventors

• Oh Eun Chu
• Kong Junjin

Classifications

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G11C16/16 Primary

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• H01L27/1157

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic