PAM-4 receiver using pattern-based clock and data recovery circuitry
US-12184290-B2 · Dec 31, 2024 · US
using a comparator for comparing the voltages obtained from two frequency to voltage converters
using a comparator for comparing the voltages obtained from two frequency to voltage converters · Cooperative Patent Classification (CPC)
Electric circuits, power, telecommunications, and semiconductors.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | H03L7/097 |
| Official title | using a comparator for comparing the voltages obtained from two frequency to voltage converters |
| Display label | using a comparator for comparing the voltages obtained from two frequency to voltage converters |
| Total patents | 195 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is declining.
| Year | Patents |
|---|---|
| 2015 | 18 |
| 2016 | 21 |
| 2017 | 7 |
| 2018 | 12 |
| 2019 | 15 |
| 2020 | 24 |
| 2021 | 27 |
| 2022 | 29 |
| 2023 | 8 |
| 2024 | 13 |
| 2025 | 18 |
| 2026 | 3 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
System and method for fast converging reference clock duty cycle correction for digital to time converter (dtc)-based analog fractional-n phase-locked loop (pll)
US-2019214976-A1 · Jul 11, 2019 · US
Digital-to-time converter and operating method thereof
US-10122378-B2 · Nov 6, 2018 · US
Adaptive clocking scheme
US-2018309455-A1 · Oct 25, 2018 · US
Track-and-hold charge pump and pll
US-2018302096-A1 · Oct 18, 2018 · US
Method and security module for receiving two signals
US-10084461-B2 · Sep 25, 2018 · US
Digital-to-time converter and operating method thereof
US-2018269895-A1 · Sep 20, 2018 · US
Clock recovery device and method
US-10044357-B1 · Aug 7, 2018 · US
Adaptive clocking scheme
US-10033391-B2 · Jul 24, 2018 · US
Phase locked loop circuit with charge pump up-down current mismatch adjustment and static phase error reduction
US-9991896-B2 · Jun 5, 2018 · US
Adaptive bandwidth systems and methods
US-2018115315-A1 · Apr 26, 2018 · US
Coherent Phase-Synchronizing Circuit
US-2018062893-A1 · Mar 1, 2018 · US
Phase Locked Loop Circuit With Charge Pump Up-Down Current Mismatch Adjustment And Static Phase Error Reduction
US-2018048322-A1 · Feb 15, 2018 · US
Method for generating unambiguous correlation function for CBOC (6,1,1/11) signal based on partial correlation functions, apparatus for tracking CBOC signals and satellite navigation signal receiver system
US-9857477-B2 · Jan 2, 2018 · US
Method and Security Module for Receiving Two Signals
US-2017294916-A1 · Oct 12, 2017 · US
Clock source, method for distributing a clock signal and integrated circuit
US-9766651-B2 · Sep 19, 2017 · US
Apparatuses, methods, and systems for jitter equalization and phase error detection
US-9735765-B2 · Aug 15, 2017 · US
CR oscillation circuit
US-9716501-B2 · Jul 25, 2017 · US
Phase-locked loop with multiple degrees of freedom and its design and fabrication method
US-9602114-B2 · Mar 21, 2017 · US
Phase lock loop lock indicator
US-9577650-B2 · Feb 21, 2017 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC H03L7/097?
- CPC H03L7/097 is the Cooperative Patent Classification code for “using a comparator for comparing the voltages obtained from two frequency to voltage converters.”
- How many patents are filed under CPC H03L7/097 (using a comparator for comparing the voltages obtained from two frequency to voltage converters)?
- Our database includes 195 publications tagged with this CPC code.
- Is patent activity under CPC H03L7/097 growing?
- Publication counts under this code: 13 in 2024 vs 18 in 2025 (latest complete years).