Charge pump calibration for dual-path phase-locked loop
US-9225345-B2 · Dec 29, 2015 · US
US8994460B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8994460-B2 |
| Application number | US-201213675650-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 13, 2012 |
| Priority date | Nov 13, 2012 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
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A method and a phase locked loop (PLL) circuit for implementing compact current mode logic inductor capacitor voltage controlled oscillator for high speed communications, and a design structure on which the subject circuit resides are provided. The PLL circuit includes a current mode logic (CML) inductor capacitor (LC) Voltage Controlled Oscillator (VCO). The PLL circuit includes a reference circuit generates a virtual ground node for biasing noise sensitive components, providing level shifted VCO increment and decrement tuning values from a phase detector coupled by a respective resistor to tune a varactor of the LC VCO, and providing a loop filter function. The virtual ground node tracks a logic power supply noise, incurring no jitter penalty, and eliminating the need for a separate power supply for the PLL circuit.
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What is claimed is: 1. A method for implementing a compact current mode logic inductor capacitor voltage controlled oscillator for high speed communications comprising: providing a PLL circuit including a current mode logic (CML) inductor capacitor (LC) Voltage Controlled Oscillator (VCO); providing a reference circuit generating a virtual ground node for biasing noise sensitive components using a logic power supply, said virtual ground node tracking logic power supply noise, in…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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