Reconfigurable electronic devices and operation method thereof

Patent metadata

Field	Value
Publication number	US-9401435-B2
Application number	US-201514828750-A
Country	US
Kind code	B2
Filing date	Aug 18, 2015
Priority date	Aug 22, 2014
Publication date	Jul 26, 2016
Grant date	Jul 26, 2016

Abstract

Provided is a reconfigurable electronic device which is implemented by forming independent upper gates and lower gates, wherein in comparison with an existing reconfigurable electronic device having the same function, a degree of integration is greatly increased, a non-volatile memory function is included in the device, and in operation of a reconfigurable circuit based on an independent lower electrode array, dynamic parasitic component is decreased and a complexity of wire lines can be reduced, so that power consumption can be reduced. In addition, in comparison with an existing reconfigurable electronic device, the device exhibits remarkably excellent performance in terms of various characteristics such as diversity of functions of a multi-functional device, alignment margin in process, performance of implementation of infinitesimal electrical doping in a channel, compatibility with bottom-up and top-down method in process, and compatibility with a 1D or 2D material.

First claim

What is claimed is:

1. A reconfigurable electronic device comprising:
a substrate;
a plurality of lower electrodes which are formed on the substrate and are electrically isolated from each other;
a lower gate insulating film which is formed on the lower electrodes;
a body which is formed on the lower gate insulating film;
a first upper electrode which is formed on a first region of the body;
a second upper electrode which is formed in a second region of the body to be separated from the first upper electrode by a predetermined distance; and
an upper gate electrode which is formed on the body or on the body and the first and second upper electrodes with an upper gate insulating film interposed therebetween,
wherein top surfaces of the lower electrodes are in contact with the lower gate insulating film, and at least one lower electrode surrounds a bottom and at least one side surface of each of the other lower electrodes.

2. The reconfigurable electronic device according to claim 1 , wherein the lower electrode surrounding the bottoms of the other lower electrodes is isolated from the substrate by an insulating film or is formed in a well shape to be electrically isolated from the substrate.

3. The reconfigurable electronic device according to claim 1 , wherein a work function or a conductivity of the lower electrode surrounding the bottom of the other lower electrodes is different from those of the other lower electrodes.

4. The reconfigurable electronic device according to claim 1 , wherein the upper gate insulating film is formed on a partial or entire region of the body or on a partial or entire region of the body and the first and second upper electrodes.

5. The reconfigurable electronic device according to claim 1 , wherein the lower electrode of which bottom is surrounded by the other lower electrode is electrically floated.

6. The reconfigurable electronic device according to claim 1 , further comprising an inter-electrode insulating film located between the lower electrodes, wherein the lower gate insulating film is formed on top surfaces of the lower electrodes and a top surface of the inter-electrode insulating film.

7. The reconfigurable electronic device according to claim 1 , wherein the lower gate insulating film is configured with a ferroelectric material, so that the lower gate insulating film can be programmed or erased according to voltages applied to the lower electrodes.

8. The reconfigurable electronic device according to claim 1 ,
wherein the lower gate insulating film is configured with at least two or more layers of insulating films, and the adjacent layers are configured with materials having different energy band gaps and dielectric constants, and
wherein at least one layer of the insulating films constituting the lower gate insulating film can store charges.

9. The reconfigurable electronic device according to claim 1 , further comprising a buffer layer for improving interface characteristics between the body and the upper gate insulating film.

10. The reconfigurable electronic device according to claim 1 , wherein two end portions of the upper gate electrode are aligned with end portions of the first and second upper electrodes with the upper gate insulating film interposed therebetween or are partially or entirely overlapped with the first and second upper electrodes with the upper gate insulating film interposed therebetween.

11. The reconfigurable electronic device according to claim 1 , wherein the body is configured with one of a 1D nano material, a 2D nano material, a metal oxide thin film, a germanium (Ge) thin film, a SiGe thin film, a silicon thin film, a III-V group compound semiconductor thin film, and a II-VI group compound semiconductor thin film.

12. An operation method for the reconfigurable electronic device according to claim 1 ,
wherein voltages are applied to the lower electrodes so that the lower gate insulating film is programmed or erased, and
wherein a degree of the programming or erasing is determined according to magnitudes or time duration of the voltages applied to the lower electrodes.

13. The operation method according to claim 12 , wherein the voltages applied to the lower electrodes are adjusted so that the degree of programming or erasing of the lower gate insulating film located under the first upper electrode and the lower gate insulating film located under the second upper electrode are changed, or one of the lower gate insulating film located under the first upper electrode and the lower gate insulating film located under the second upper electrode is programmed and the other is erased.

14. The operation method according to claim 12 , wherein the same voltage is applied to the first and second lower electrodes located under the first and second upper electrodes so that the lower gate insulating film is programmed or erased.

15. The operation method according to claim 12 ,
wherein in the programming or erasing, the same voltage (including 0 V) is applied to the first and second upper electrodes,
wherein a voltage is applied to the upper gate electrode but current is not flowed between the first and second upper electrodes, or
wherein a voltage is applied to the upper gate electrode and current is flowed between the first and second upper electrodes.

16. The operation method according to claim 12 , wherein, prior to a procedure of the programming or the erasing, a predetermined voltage is applied to the upper gate electrode, or light is applied to the upper gate electrode.

17. The operation method according to claim 12 ,
wherein voltages of the respective lower electrodes located under the first and second upper electrodes are adjusted to induce holes to one side of the body under the lower electrodes and induce electrons to the other side, so that the reconfigurable electronic device is operated as a p-n or n-p diode, or
wherein an additional lower electrode exists between the lower electrodes located under the first and second upper electrodes, a voltage of the lower electrode is adjusted to maintain neutrality of the body on the lower electrode or to induce electrons or holes to the body, so that the reconfigurable electronic device is operated as a p-n or n-p diode.

18. The operation method according to claim 12 ,
wherein voltages applied to the lower electrodes located under the first and second upper electrodes are adjusted to induce an electron layer to the body, so that the reconfigurable electronic device is operated as an n-type MOSFET or to induce a hole layer to the body, so that the reconfigurable electronic device is operated as a p-type MOSFET, or
wherein an additional lower electrode exists between the lower electrodes located under the first and second upper electrodes, a voltage of the lower electrode is adjusted to maintain neutrality of the body on the lower electrode or to induce electrons or holes to the body, so that a threshold voltage value of a MOSFET is changed for operation.

19. A reconfigurable electronic device comprising:
a substrate;
one or two or more lower electrodes which are formed on the substrate and are electrically isolated from each other;
a lower gate insulating film which is formed on a partial region of the substrate and the lower electrodes;
a body which is formed on the lower gate insulating film;
a first upper electrode which is formed on a first region of the body;
a second upper electrode which is formed on a second region of the body to be separated from the first upper electrode by a predetermined dis

Assignees

• Snu R&Db Foundation

Inventors

• Lee Jong-Ho

Classifications

• H10D30/701

  IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs · CPC title

• H10D30/699

  having the gate at least partly formed in a trench · CPC title

• H10D30/697

  having trapping at multiple separated sites, e.g. multi-particles trapping sites · CPC title

• H10D30/696

  having at least one additional gate, e.g. program gate, erase gate or select gate · CPC title

• H10D30/694

  characterised by the shapes, relative sizes or dispositions of the gate electrodes · CPC title