Memory control device and a delay controller

Patent metadata

Field	Value
Publication number	US-9396789-B2
Application number	US-201514879925-A
Country	US
Kind code	B2
Filing date	Oct 9, 2015
Priority date	Jun 11, 2013
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

A memory control device includes a plurality of delay circuits to set a delay value for each terminal of a memory, each of the plurality of delay circuits being connected to a terminal of the memory. Further, the memory control device includes a first register to store a first DLL value output by a delay locked loop circuit, a plurality of second registers to store a first setting value to set the delay value for the each terminal of the memory, each of the plurality of second registers being connected to a delay circuit of the plurality of delay circuits, and a delay controller to calculate a second setting value based on the first DLL value, a second DLL value output by the delay locked loop circuit after the first DLL value, and the first setting value, and to update the first setting value to the second setting value.

First claim

The invention claimed is:

1. A memory control device including a delay locked loop circuit, the memory control device comprising:
a plurality of delay circuits to set a delay value for each terminal of a memory, each of the plurality of delay circuits being connected to a terminal of the memory;
a first register to store a first DLL value output by the delay locked loop circuit;
a plurality of second registers to store a first setting value to set the delay value for the each terminal of the memory, each of the plurality of second registers being connected to a delay circuit of the plurality of delay circuits; and
a delay controller to calculate a second setting value based on the first DLL value, a second DLL value output by the delay locked loop circuit after the first DLL value, and the first setting value, and to update the first setting value to the second setting value, wherein
the delay controller calculates the second setting value at n times, where n is a natural number equal to or greater than 1, using the following equation,
B n =( B n-1 /A n-1 )× A n

the A n-1 is the first DLL value set at n−1 times,
the B n-1 is the first setting value set at the n−1 times,
the A n is the second DLL value set at n times, and
the B n is the second setting value set at the n times.

2. The memory control device of claim 1 , wherein the delay controller detects a difference between the first DLL value and the second DLL value, and determines whether or not to perform the calculation of the second setting value according to an amount of the difference.

3. The memory control device of claim 1 , further comprising:
a write leveling controller to input a strobe signal, the write leveling controller being connected to a second register of the plurality of second registers corresponding to a terminal of the memory, and the write leveling controller setting the delay value in response to a write leveling command to the second register.

4. The memory control device of claim 1 , wherein a number of the plurality of second registers is a same as a number of the plurality of delay circuits.

5. The memory control device of claim 1 , wherein the delay controller includes a subtractor and an adder with a bit shifter.

6. The memory control device of claim 1 , further comprising:
a timing generator to control timing of a calibration execution of the delay locked loop circuit.

7. The memory control device of claim 6 , wherein the timing generator is configured to output a timing signal synchronized with a refresh cycle of the memory based on a refresh flag to the delay controller.

8. The memory control device of claim 6 , wherein the timing generator is connected to a temperature sensor.

9. A memory control device comprising:
a memory controller to control a memory;
a delay locked loop circuit;
a plurality of delay circuits to set a delay value for each terminal of the memory, each of the plurality of delay circuits being connected to a terminal of the memory;
a first register to store a first DLL value output by the delay locked loop circuit;
a plurality of second registers to store a first setting value to set the delay value for the each terminal of the memory, each of the plurality of second registers being connected to a delay circuit of the plurality of delay circuits; and
a delay controller to calculate a second setting value based on the first DLL value, a second DLL value output by the delay locked loop circuit after the first DLL value, and the first setting value, and to update the first setting value to the second setting value, wherein
the delay controller calculates the second setting value at n times, where n is a natural number equal to or greater than 1, using the following equation,
B n =( B n-1 /A n-1 )× A n

the A n-1 is the first DLL value set at n−1 times,
the B n-1 is the first setting value set at the n−1 times,
the A n is the second DLL value set at n times, and
the B n is the second setting value set at the n times.

10. A delay controller including a delay locked loop circuit, the delay controller comprising:
a plurality of delay circuits to set a delay value for each terminal of a memory, each of the plurality of delay circuits being connected to a terminal of the memory;
a first register to store a first DLL value output by the delay locked loop circuit;
a plurality of second registers to store a first setting value to set the delay value for the each terminal of the memory, each of the plurality of second registers being connected to a delay circuit of the plurality of delay circuits; and
a delay control circuit to calculate a second setting value based on the first DLL value, a second DLL value output by the delay locked loop circuit after the first DLL value, and the first setting value, and to update the first setting value to the second setting value, wherein
the delay controller calculates the second setting value at n times, where n is a natural number equal to or greater than 1, using the following equation,
B n =( B n-1 /A n-1 )× A n

the A n-1 is the first DLL value set at n−1 times,
the B n-1 is the first setting value set at the n−1 times,
the A n is the second DLL value set at n times, and
the B n is the second setting value set at the n times.

Assignees

• Iwasaki Keiichi
• Ricoh Co Ltd

Inventors

• Iwasaki Keiichi

Classifications

• G11C2207/2254

  Calibration · CPC title

• G11C11/406

  Management or control of the refreshing or charge-regeneration cycles · CPC title

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G06F13/42

  Bus transfer protocol, e.g. handshake; Synchronisation · CPC title

• G11C11/4076 Primary

  Timing circuits (for regeneration management G11C11/406) · CPC title