Memory devices having source lines directly coupled to body regions and methods
US-2024386966-A1 · Nov 21, 2024 · US
US8958249B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8958249-B2 |
| Application number | US-201414195282-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 3, 2014 |
| Priority date | Mar 4, 2013 |
| Publication date | Feb 17, 2015 |
| Grant date | Feb 17, 2015 |
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A set of memory cells can be erased by individually erasing portions of the set in order to normalize the erase behavior of each memory cell and provide more consistent erase rates. An erase voltage pulse can be applied to the set of memory cells with a first group of cells biased for erase and a second group biased to inhibit erase. The erase depth is made shallower as the device is cycled more.
Opening claim text (preview).
What is claimed is: 1. A method of operating non-volatile storage, the method comprising: erasing a group of non-volatile storage elements that are arranged as NAND strings; programming a set of the non-volatile storage elements in the group after erasing the group; determining erase-state to A-state fails in the set of the non-volatile storage elements after the programming; establishing a dynamic erase depth for erasing the group of non-volatile storage elements based on t…
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