Power savings apparatus and method for memory device using delay locked loop

Patent metadata

Field	Value
Publication number	US-9047237-B2
Application number	US-201213566187-A
Country	US
Kind code	B2
Filing date	Aug 3, 2012
Priority date	Aug 3, 2012
Publication date	Jun 2, 2015
Grant date	Jun 2, 2015

Abstract

Embodiments are directed to reduced power consumption for memory data transfer at high frequency through synchronized clock signaling. Delay locked loop (DLL) circuits are used to generate the synchronized clock signals. A DLL circuit consumes power as long as it is outputting the synchronized clock signals. A power saving apparatus and method are described wherein the DLL circuit is powered on when memory data access is active, while the DLL circuit is powered down when memory access is idle.

First claim

What is claimed is:

1. A memory apparatus, comprising:
a delay locked loop (DLL) having a DLL lock time;
a memory device having an initial data access latency time; and
a memory controller having a controller latency time, and configured to receive a memory access instruction, the memory controller providing a DLL turn-on command to the DLL based on receipt of the memory access instruction, the controller latency time, the initial data access latency time and the DLL lock time,
wherein the sum of controller latency time and initial data access latency time exceeds the DLL lock time.

2. The memory apparatus of claim 1 , wherein the DLL is in a locked state when valid data is on a data bus, the data bus configured to provide coupling between the memory device and the memory controller.

3. The memory apparatus of claim 1 , wherein the DLL outputs a clock signal (clk0) and a clock-90 (clk90) signal that is 90 degrees ahead in phase to the clock signal (clk0).

4. The memory apparatus of claim 1 , wherein the DLL receives the DLL turn-on command via a reset signal port.

5. The memory apparatus of claim 1 , wherein the DLL outputs a plurality of synchronized clock signals, wherein each clock signal is shifted in phase from the other clock signals, the plurality of synchronized clock signals being one of 4, 8, and 16 synchronized clock signals.

6. The memory apparatus of claim 1 , wherein the DLL reverts to a powered-down state following completion of the memory access instruction.

7. The memory apparatus of claim 1 , further comprising:
a counter coupled to the DLL, the counter being configured to delay receipt of the DLL turn-on command by a delay that does not exceed the excess of the sum of controller latency time and initial data access latency time over the DLL lock time.

8. The memory apparatus of claim 1 , wherein the memory access instruction comprises a memory read instruction and a memory write instruction.

9. The memory apparatus of claim 1 , further comprising a CPU coupled to the memory controller via an internal system bus.

10. The memory apparatus of claim 1 , further comprising:
a dynamic counter coupled to the DLL, wherein the dynamic counter is configured to delay receipt of the DLL turn-on command by a delay that does not exceed the excess of the sum of controller latency time and initial data access latency time over the DLL lock time, and wherein the dynamic counter is configured to respond to real-time changes in one or more of the controller latency time and the initial data access latency time.

11. A method, comprising:
receiving a memory access instruction at a memory apparatus, the memory apparatus comprising a memory device having an initial data access latency time, a delay locked loop (DLL) having a DLL lock time, and a memory controller having a controller latency time;
generating a DLL turn-on command based on the receipt of the memory access instruction, the controller latency time, the initial data access latency time and the DLL lock time;
locking the DLL in response to receiving the DLL turn-on command; and
delaying locking the DLL based on the excess of the sum of controller latency time and initial data access latency time over the DLL lock time.

12. The method of claim 11 , wherein the locking the DLL has completed and resulted in a locked state when valid data is on a data bus, the data bus configured to provide coupling between the memory device and the memory controller.

13. The method of claim 11 , further comprising outputting a clock signal (clk0) and a clock-90 signal (clk90) that is 90 degrees ahead in phase to the clock signal (clk0).

14. The method of claim 11 , wherein the locking the DLL in response to receiving the DLL turn-on command includes receiving the DLL turn-on command via a reset signal port.

15. The method of claim 11 , further comprising outputting a plurality of synchronized clock signals, wherein each clock signal is shifted in phase from the other clock signals, the plurality of synchronized clock signals being one of 4, 8, and 16 synchronized clock signals.

16. The method of claim 11 , further comprising accessing the memory device after the locking the DLL is complete.

17. The method of claim 11 , further comprising: reverting DLL to a powered-down state following completion of the memory access instruction.

18. The method of claim 11 , wherein the delaying includes using a counter.

19. The method of claim 11 , further comprising: decoding the memory access instruction.

20. The method of claim 11 , wherein the delaying includes using a dynamic counter that can respond to real-time changes in one or more of the controller latency time and the initial data access latency time.

21. A system, comprising a memory apparatus, the memory apparatus comprising:
a delay locked loop (DLL) having a DLL lock time;
a memory device having an initial data access latency time; and
a memory controller having a controller latency time, and configured to receive a memory access instruction, the memory controller providing a DLL turn-on command to the DLL based on receipt of the memory access instruction, the controller latency time, the initial data access latency time and the DLL lock time,
wherein the sum of controller latency time and initial data access latency time exceeds the DLL lock time.

Assignees

• Hasan Qamrul
• Zitlaw Clifford
• Rosner Stephan
• Dubois Sylvain
• Cypress Semiconductor Corp

Inventors

• Hasan Qamrul
• Zitlaw Clifford
• Rosner Stephan
• Dubois Sylvain

Classifications

• G06F13/16 Primary

  for access to memory bus (G06F13/28 takes precedence) · CPC title

• Y02B60/1225

  Cross-Sectional Technologies · mapped topic

• G06F1/3275 Primary

  Power saving in memory, e.g. RAM, cache · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G11C8/00 Primary

  Arrangements for selecting an address in a digital store (for stores using transistors G11C11/407, G11C11/413) · CPC title