Semiconductor devices having plug insulators

Patent metadata

Field	Value
Publication number	US-9390961-B2
Application number	US-201414481932-A
Country	US
Kind code	B2
Filing date	Sep 10, 2014
Priority date	Dec 13, 2013
Publication date	Jul 12, 2016
Grant date	Jul 12, 2016

Abstract

Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a first bit line structure extending in a first direction, a second bit line structure extending in the first direction and spaced apart from the first bit line structure, a storage contact plug located between the first bit line structure and the second bit line structure, and extending in a second direction perpendicular to the first direction, a first plug insulator located between the first bit line structure and the second bit line structure, and configured to contact a side surface extending in the second direction of the storage contact plug, and a plug isolation pattern located between the first bit line structure and the first plug insulator.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first bit line structure extending in a first direction;
a second bit line structure extending in the first direction, the second bit line structure spaced apart from the first bit line structure in a second direction that is different from the first direction;
a storage contact plug between the first bit line structure and the second bit line structure;
a first plug insulator between the first bit line structure and the second bit line structure, the first plug insulator directly contacting a first side surface of the storage contact plug that extends in the second direction and not directly contacting a second side surface of the storage contact plug that extends in the second direction, the second side surface being opposite the first side surface; and
a plug isolation pattern between the first bit line structure and the first plug insulator,
wherein the first plug insulator and the plug isolation pattern are adjacent each other along the second direction and the storage contact plug and the plug isolation pattern are adjacent each other along the first direction wherein the plug isolation pattern directly contacts the first side surface of the storage contact plug and wherein a profile of a side surface of the first plug insulator that directly contacts the storage contact plug is different from a profile of a side surface of the plug isolation pattern that directly contacts the storage contact plug.

2. The semiconductor device of claim 1 , wherein the first plug insulator includes a first side surface facing the second bit line structure and a second side surface facing the plug isolation pattern, and a length in the first direction of a first side surface of the first plug insulator is greater than a length in the first direction of a second side surface of the first plug insulator.

3. The semiconductor device of claim 1 , wherein the first plug insulator has a first length in the second direction and the plug isolation pattern has a second length in the second direction that is greater than the first length.

4. The semiconductor device of claim 1 , further comprising:
a first bit line spacer on a side surface of the first bit line structure; and
a second bit line spacer on a side surface of the second bit line structure,
wherein the plug isolation pattern is in direct contact with the first bit line spacer, and the first plug insulator is spaced apart from the plug isolation pattern and the second bit line spacer, and
wherein the storage contact plug directly contacts both the first bit line spacer and the second bit line spacer.

5. The semiconductor device of claim 4 , wherein a first distance in the second direction between the first plug insulator and the plug isolation pattern is the same as a second distance in the second direction between the first plug insulator and the second bit line spacer.

6. The semiconductor device of claim 4 , further comprising:
a second plug insulator configured to fill a first space between the first plug insulator and the plug isolation pattern and a second space between the first plug insulator and the second bit line spacer,
wherein an etch rate of the second plug insulator is different than an etch rate of the first plug insulator.

7. The semiconductor device of claim 6 , wherein the storage contact plug is in contact with the plug isolation pattern and the second plug insulator, and wherein a profile of a side surface of the plug isolation pattern that is in contact with the storage contact plug is different than a profile of a side surface of the second plug insulator that is in contact with the storage contact plug.

8. A semiconductor device, comprising:
a first bit line structure on a semiconductor substrate;
a first bit line spacer on a side surface of the first bit line structure;
a second bit line structure on the semiconductor substrate that is spaced apart from the first bit line structure, an upper portion of at least part of the second bit line structure that extends farther above an upper surface of the semiconductor substrate than a lower portion of the second bit line structure being bent toward the first bit line structure to be closer to the first bit line structure than is at least part of the lower portion of the second bit line structure;
a second bit line spacer on a side surface of the second bit line structure;
a plug isolation pattern between the first bit line spacer and the second bit line spacer; and
a plug insulator between the second bit line spacer and the plug isolation pattern,
wherein an upper surface of the plug isolation pattern and an upper surface of the second bit line spacer are farther above an upper surface of the semiconductor substrate than is an upper surface of the plug insulator.

9. The semiconductor device of claim 8 , wherein the upper surface of the plug isolation pattern is coplanar with the upper surface of the second bit line structure.

10. The semiconductor device of claim 8 , wherein a lower surface of the plug insulator is farther above an upper surface of the semiconductor substrate than is a lower surface of the plug isolation pattern.

11. The semiconductor device of claim 10 , wherein the lower surface of the plug isolation pattern is substantially coplanar with an upper surface of the semiconductor substrate.

12. The semiconductor device of claim 10 , wherein the plug insulator is spaced apart from the plug isolation pattern, and wherein a horizontal distance between the plug insulator and the plug isolation pattern is the same as a vertical distance between an upper surface of the semiconductor substrate and the plug insulator.

13. The semiconductor device of claim 12 ,
wherein the second bit line spacer is spaced apart from the plug insulator, and
wherein a horizontal distance between the plug insulator and the second bit line spacer is the same as a vertical distance between the upper surface of the semiconductor substrate and the plug insulator.

14. The semiconductor device of claim 8 , further comprising a storage contact plug, wherein both the plug isolation pattern and the plug insulator directly contact the storage contact plug.

15. A semiconductor device, comprising:
a first bit line structure that extends along an upper surface of a semiconductor substrate in a first direction and that extends upwardly from the upper surface of the semiconductor substrate;
a second bit line structure that extends along the upper surface of the semiconductor substrate in the first direction and that extends upwardly from the upper surface of the semiconductor substrate;
a first bit line spacer that extends along a side surface of the first bit line structure in the first direction; and
a plug insulator adjacent the first bit line spacer opposite the first bit line structure,
wherein an upper portion of the first bit line spacer is closer to the second bit line structure than is a lower portion of the first bit line spacer so that the upper portion of the first bit line spacer extends at least partly over an upper portion of the plug insulator that is directly underneath the first bit line spacer wherein the side surface of the first bit line structure comprises a first side surface, the semiconductor device further comprising a second bit line spacer that extends along a second side surface of the first bit line structure that is opposite the first side surface, wherein no plug insulator is provided adjacent to the second bit line spacer.

16. The semiconductor device of claim 15 , further comprising:
a second bit lin

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Mong-Sup
• Gwak Byoung-Yong
• Kwak Byung-Ho
• Kim Yoon-Kyung
• Park Tae-Joon
• Ryu Byung-Sul
• Hwang In-Seak

Classifications

• H10W10/011 Primary

  of isolation regions comprising dielectric materials · CPC title

• H10W10/10 Primary

  Isolation regions comprising dielectric materials · CPC title

• H10B12/0335

  Making a connection between the transistor and the capacitor, e.g. plug · CPC title

• H10B12/482

  Bit lines · CPC title

• H10B99/00

  Subject matter not provided for in other groups of this subclass · CPC title