Integrated circuit having voltage mismatch reduction

Patent metadata

Field	Value
Publication number	US-9390816-B2
Application number	US-201514980250-A
Country	US
Kind code	B2
Filing date	Dec 28, 2015
Priority date	Nov 12, 2014
Publication date	Jul 12, 2016
Grant date	Jul 12, 2016

Abstract

An integrated circuit has a first circuit portion on a first level and a second circuit portion on a second level different from the first level. The first circuit portion includes a first cell having a first voltage value at a first node and a second voltage value at a second node. The second circuit portion includes a second cell coupled with the first cell, the second cell being selectively controllable to supply a voltage to the first cell based on an instruction to supply the voltage. The instruction to supply the voltage is based on a determined mismatch between the first voltage value and the second voltage value being greater than a predetermined threshold value.

First claim

What is claimed is:

1. An integrated circuit comprising:
a first circuit portion on a first level, the first circuit portion comprising a first cell configured to have a first voltage value at a first node and a second voltage value at a second node; and
a second circuit portion on a second level different from the first level, the second circuit portion comprising a second cell coupled with the first cell, the second cell being selectively controllable to supply a voltage to the first cell based on an instruction to supply the voltage,
wherein the instruction to supply the voltage is based on a determined mismatch between the first voltage value and the second voltage value being greater than a predetermined threshold value.

2. The integrated circuit of claim 1 , wherein the first cell comprises a bit cell.

3. The integrated circuit of claim 1 , wherein the first cell comprises a sense amplifier.

4. The integrated circuit of claim 3 , wherein the first cell further comprises a bit cell.

5. The integrated circuit of claim 1 , wherein the integrated circuit is configured to apply the voltage to at least one of the first node or the second node.

6. The integrated circuit of claim 1 , wherein the second cell comprises a transistor configured to be selectively turned on or off to supply the voltage to the first cell.

7. The integrated circuit of claim 1 , wherein the first cell comprises a transistor configured to receive the voltage, and the voltage changes a voltage ratio of the transistor.

8. The integrated circuit of claim 1 , wherein the first circuit portion has a first surface area in a first plane and the second circuit portion has a second surface area in a second plane parallel to the first plane.

9. The integrated circuit of claim 1 , wherein the first cell of the first circuit portion has a layout in compliance with a first set of process design rules and the second cell of the second circuit portion has a layout in compliance with a second set of process design rules.

10. The integrated circuit of claim 1 , wherein the second level comprises a decoder configured to select the second cell.

11. An apparatus comprising:
a memory including computer program code for one or more programs; and
a processor configured to execute an instruction from the memory to cause the apparatus to:
detect a first voltage value at a first node of a first cell of a first circuit portion, the first circuit portion being on a first level of an integrated circuit;
detect a second voltage value at a second node of the first cell; and
based on a determined mismatch between the first voltage value and the second voltage value being greater than a predetermined threshold value, instruct a second cell to supply a voltage to the first cell, the second cell belonging to a second circuit portion on a second level different from the first level.

12. The apparatus of claim 11 , wherein instructing the second cell to supply the voltage comprises selecting the second cell with a decoder.

13. The apparatus of claim 11 , wherein instructing the second cell to supply the voltage to the first cell comprises supplying the voltage to at least one of the first node or the second node.

14. The apparatus of claim 11 , wherein the first cell comprises at least one of a bit cell or a sense amplifier.

15. A method comprising:
detecting a first voltage value at a first node of a first cell of a first circuit portion, the first circuit portion being on a first level of an integrated circuit;
detecting a second voltage value at a second node of the first cell; and
based on a determined difference between the first voltage value and the second voltage value being greater than a predetermined threshold value, instructing a second cell to supply a voltage to the first cell, the second cell belonging to a second circuit portion on a second level different from the first level.

16. The method of claim 15 , wherein supplying the voltage to the first cell changes a voltage ratio of a transistor of the first cell.

17. The method of claim 15 , wherein supplying the voltage to the first cell increases a voltage threshold value of the first circuit portion.

18. The method of claim 15 , wherein supplying the voltage to the first cell reduces a minimum operating voltage value of the first circuit portion.

19. The method of claim 15 , wherein supplying the voltage to the first cell causes the mismatch between the first voltage value and the second voltage value to be less than the predetermined threshold value.

20. The method of claim 15 , wherein supplying the voltage to the first cell comprises supplying the voltage to at least one of a bit cell or a sense amplifier.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Hsu Yu-Hao
• Huang Chia-En
• Huang Hektor
• Chang Yi-Ching
• Yang Chen-Lin
• Yang Jung-Ping
• Lee Cheng Hung

Classifications

• G11C29/702 Primary

  by replacing auxiliary circuits, e.g. spare voltage generators, decoders or sense amplifiers, to be used instead of defective ones · CPC title

• G11C11/413

  Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction · CPC title

• G11C11/417

  for memory cells of the field-effect type · CPC title

• G11C11/419 Primary

  Read-write [R-W] circuits · CPC title