Epitaxial substrate for semiconductor device, semiconductor device, and method of manufacturing epitaxial substrate for semiconductor device

Patent metadata

Field	Value
Publication number	US-9382641-B2
Application number	US-76704110-A
Country	US
Kind code	B2
Filing date	Apr 26, 2010
Priority date	May 12, 2009
Publication date	Jul 5, 2016
Grant date	Jul 5, 2016

Abstract

An epitaxial substrate having preferable two dimensional electron gas characteristic and contact characteristic is provided in the present invention. A channel layer is formed on a base substrate with GaN. A spacer layer is formed on the channel layer with AlN. A barrier layer is formed on the spacer layer with group III nitride having a composition of In X Al y Ga z N (wherein x+y+z=1) and at least including In, Al, and Ga such that the composition of the barrier layer is within the range surrounded with four lines defined in accordance with the composition on a ternary phase diagram with InN, AlN, and GaN as vertexes.

First claim

What is claimed is:

1. An epitaxial substrate for a semiconductor device, comprising:
a base substrate;
a channel layer made of GaN, formed on said base substrate;
a spacer layer made of a group III nitride having a composition of Al p Ga 1−p N (wherein 0.8≦p≦1), formed on said channel layer; and
a barrier layer made of a group III nitride having a composition of In a Al b Ga c N (wherein a+b+c=1), formed on said spacer layer, said group III nitride of said barrier layer including at least In, Al, and Ga;
wherein the spacer layer consists of a single material composition layer formed directly on the channel layer,
wherein the barrier layer consists of a single material composition layer formed directly on the spacer layer,
wherein the entirety of a surface of each of the channel layer, the spacer layer and the barrier layer are parallel to a surface of the base substrate,
wherein said channel layer, said spacer layer and said barrier layer are epitaxially formed in this order on said base substrate; and
wherein a composition of said group III nitride of said barrier layer is within a range surrounded with lines represented by the following formulas on a ternary phase diagram with InN, AlN, and GaN as vertexes
4 x=y= 0.8(1− z ),

19 x=y= 0.95(1− z ),

z=0.6, and
z=0.4,

wherein x, y and z represent respective axes of the ternary phase diagram, and wherein x, y and z respectively correspond to In, Al and Ga content of the composition of In a Al b Ga c N, and
wherein a two dimensional electron gas concentration is no less than 1.6×10 13 cm −2 .

2. The epitaxial substrate for a semiconductor device according to claim 1 , wherein said spacer layer is made of AlN.

3. The epitaxial substrate for a semiconductor device according to claim 1 , wherein said base substrate is a sapphire substrate.

4. A semiconductor device comprising:
a base substrate;
a channel layer made of GaN, formed on said base substrate;
a spacer layer made of a group III nitride having a composition of Al p Ga 1−p N (wherein 0.8≦p≦1), formed on said channel layer;
a barrier layer made of a group III nitride having a composition of In a Al b Ga c N (wherein a+b+c=1), formed on said spacer layer, said group III nitride of said barrier layer including at least In, Al, and Ga; and
a source electrode, a drain electrode, and a gate electrode provided on said barrier layer;
wherein the spacer layer consists of a single material composition layer formed directly on the channel layer,
wherein the barrier layer consists of a single material composition layer formed directly on the spacer layer,
wherein the entirety of a surface of each of the channel layer, the spacer layer and the barrier layer are parallel to a surface of the base substrate,
wherein said channel layer, said spacer layer and said barrier layer are epitaxially formed in this order on said base substrate; and
wherein a composition of said group III nitride of said barrier layer is within a range surrounded with lines represented by the following formulas on a ternary phase diagram with InN, AIN, and GaN as vertexes
4 x=y= 0.8(1− z ),

19 x=y= 0.95(1 −z )
z=0.6
z=0.4

wherein x, y and z represent respective axes of the ternary phase diagram, and wherein x, y and z respectively correspond to In, Al and Ga content of the composition of In a Al b Ga c N, and
wherein a two dimensional electron gas concentration is no less than 1.6×10 13 cm −2 .

5. The semiconductor device according to claim 4 , wherein said spacer layer is made of AlN.

6. The semiconductor device according to claim 4 , wherein said base substrate is a sapphire substrate.

7. A method of manufacturing an epitaxial substrate for a semiconductor device, comprising the steps of:
a) epitaxially forming a channel layer made of GaN on a base substrate;
b) epitaxially forming a spacer layer made of group III nitride having a composition of Al p Ga 1−p N (wherein 0.8≦p<1) on said channel layer, and
c) epitaxially forming a barrier layer made of group III nitride having a composition of In x Al y Ga z N (wherein x+y+z=1) on said spacer layer, said group III nitride including at least In, Al, and Ga,
wherein the spacer layer consists of a single material composition layer formed directly on the channel layer,
wherein the barrier layer consists of a single material composition layer formed directly on the spacer layer,
wherein the entirety of a surface of each of the channel layer, the spacer layer and the barrier layer are parallel to a surface of the base substrate,
wherein said channel layer, said spacer layer and said barrier layer are epitaxially formed in this order on said base substrate; and
wherein in said step c), the composition of said group III nitride is selected within the range surrounded with the lines represented by the following formulas defined in accordance with the composition of said group III nitride on a ternary phase diagram with InN, AN, and GaN as vertexes
4 x=y= 0.8(1− z ),

19 x=y= 0.95(1 −z )
z=0.6
z=0.4

wherein x, y and z represent respective axes of the ternary phase diagram, and wherein x, y and z respectively correspond to In, Al and Ga content of the composition of In a Al b Ga c N, and wherein a two dimensional electron gas concentration is no less than 1.6 ×10 13 cm −2 .

8. The method of manufacturing an epitaxial substrate for a semiconductor device according to claim 7 , wherein an atmosphere gas other than a material gas in said step c) is nitrogen gas.

9. The method of manufacturing an epitaxial substrate for a semiconductor device according to claim 7 , wherein the formation temperature of said spacer layer in said step b) is substantially same as that of said channel layer in said step a), and the formation temperature of said barrier layer in said step c) is lower than that of said channel layer.

10. The method of manufacturing an epitaxial substrate for a semiconductor device according to claim 9 , wherein
the formation temperature T 1 (° C.) of said channel layer is determined within the range of 1000° C.≦T 1 ≦1200° C., and
the formation temperature T 2 (° C.) of said barrier layer is determined within the range of 650° C.≦T 2 ≦900° C.

11. The method of manufacturing an epitaxial substrate for a semiconductor device according to claim 7 , wherein the pressure in a reactor in said step c) is no less than 1 kPa and no more than 30 kPa.

12. The method of manufacturing an epitaxial substrate for a semiconductor device according to claim 11 , wherein the pressure in the reactor in said step c) is no less than 1 kPa and no more than 20 kPa.

13. The method of manufacturing an epitaxial substrate for a semiconductor device according to claim 7 , wherein the V/III ratio in said step c) is no less than 5000 and no more than 20000.

14. The method of manufacturing an epitaxial substrate for a semiconductor device according to claim 7 , wherein said spacer layer is formed of MN in said step b).

15. The method of manufacturing an epitaxial substrate for a semiconductor device according to claim 7 , wherein a sapphire substrate is used for said base substrate.

16. The epitaxial substrate for a semiconductor device according to claim 1 , wherein a root mean square roughness of a heterojunction interface between said channel layer and said spacer layer is in a range of 0.1 nm and 3 nm.

Assignees

• Ichimura Mikiya
• Miyoshi Makoto
• Tanaka Mitsuhiro
• Ngk Insulators Ltd

Inventors

• Ichimura Mikiya
• Miyoshi Makoto
• Tanaka Mitsuhiro

Classifications

• H10P14/3416

  Nitrides · CPC title

• H10P14/3216

  Nitrides · CPC title

• H10P14/2921

  being crystalline insulating materials · CPC title

• H10P14/2901

  Materials · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title