Memory depth optimization in communications systems with ensemble PHY layer requirements

Patent metadata

Field	Value
Publication number	US-9379741-B2
Application number	US-37060009-A
Country	US
Kind code	B2
Filing date	Feb 13, 2009
Priority date	Feb 13, 2008
Publication date	Jun 28, 2016
Grant date	Jun 28, 2016

Abstract

Memory depth optimization in communications systems with ensemble PHY layer requirements. Memory depth, for one or more modules in a communication device, is managed based on a limited amount of provisioned hardware. For example, each of a number of various modules within a communication device is configurable to operate at various memory depths. Considered together, various sets or profiles of operational parameters (e.g., associated with particular settings for each of the various modules within the communication device), may be employed to configure the communication device to operate in accordance with one of a variety of operational modes. For example, in a first operational mode, latency may be minimized (e.g., using shorted codewords, shorter interleaver depth, etc.), whereas in a second operational mode, a higher latency may be tolerated but with an expectation of much lower error rates (e.g., achieved using more powerful ECC, longer interleaver depth, etc.).

First claim

What is claimed is:

1. An apparatus comprising:
an encoder to encode a plurality of information bits in accordance with any one of a plurality of memory depths thereby generating a plurality of signals;
a processor, coupled to the encoder, to perform memory optimization including selecting a corresponding memory depth employed by the encoder for generating each of the plurality of signals; and
a transmitter, coupled to at least one communication channel, to transmit the plurality of signals respectively via a plurality of service flows, wherein the plurality of memory depths is limited by a predetermined total memory depth that allows at least one but less than all of the plurality of signals to be encoded in accordance with a maximum per signal memory depth.

2. The apparatus of claim 1 , wherein:
the processor is coupled to the transmitter; and
based on the predetermined total memory depth, the processor directs the transmitter to:
transmit a first service flow of the plurality of service flows at a first bit rate; and
transmit a second service flow of the plurality of service flows at a second bit rate.

3. The apparatus of claim 1 , wherein:
based on the predetermined total memory depth, the processor directs the encoder to:
encode at least some of the plurality of information bits in accordance with a first memory depth thereby generating a first signal of the plurality of signals; and
encode at least some of the plurality of information bits in accordance with a second memory depth thereby generating a second signal of the plurality of signals.

4. The apparatus of claim 3 , wherein:
the first memory depth includes at least one of a first code rate, a first block size, a first symbol mapping, a first interleaver depth, and a first bit rate; and
the second memory depth includes at least one of a second code rate, a second block size, a second symbol mapping, a second interleaver depth, and a second bit rate.

5. The apparatus of claim 3 , wherein:
the first memory depth includes a first code rate, a first block size, a first symbol mapping, a first interleaver depth, and a first bit rate; and
the second memory depth includes a second code rate, a second block size, a second symbol mapping, a second interleaver depth, and a second bit rate.

6. The apparatus of claim 1 , wherein the encoder further comprises a variable interleaver, wherein:
the variable interleaver is operative to interleave the plurality of information bits in accordance with any one of a plurality of interleaver memory depths; and
based on the predetermined total memory depth, the processor selects a corresponding interleaver memory depth employed by the variable interleaver for interleaving at least some of the plurality of information bits.

7. The apparatus of claim 1 , wherein the encoder further comprises a plurality of interleavers, wherein:
a first interleaver of the plurality of interleavers is operative to interleave a first portion of the plurality of information bits in accordance with a first interleaver memory depth;
a second interleaver of the plurality of interleavers is operative to interleave a second portion of the plurality of information bits in accordance with a second interleaver memory depth; and
based on the predetermined total memory depth, the processor selects the first interleaver memory depth and the second interleaver memory depth.

8. The apparatus of claim 1 , wherein the encoder further comprises a symbol mapper, wherein:
each of the plurality of signals includes a corresponding plurality of symbols;
the symbol mapper is operative to map each symbol of each of the corresponding plurality of symbols to a respective constellation having a corresponding mapping of constellation points therein; and
based on the predetermined total memory depth, the processor selects a constellation and corresponding mapping by which at least one symbol of at least one of the corresponding plurality of symbols is mapped.

9. The apparatus of claim 8 , wherein at least two symbols of the corresponding plurality of symbols are mapped to a common, respective constellation having a corresponding mapping of constellation points therein.

10. The apparatus of claim 1 , wherein:
the encoder is operative to:
encode a first portion of the plurality of information bits thereby generating a first codeword having a first codeword size; and
encode a second portion of the plurality of information bits thereby generating a second codeword having a second codeword size;

each of the plurality of memory depths, by which the encoder is operative to perform encoding, corresponds to a respective codeword size; and
based on the predetermined total memory depth, the processor selects the first codeword size and the second codeword size.

11. The apparatus of claim 1 further comprising:
a plurality of encoders, and wherein:
the processor is coupled to each of the plurality of encoders;
the encoder is one of the plurality of encoders;
a first encoder of the plurality of encoders is operative to encode a first portion of the plurality of information bits thereby generating a first codeword having a first codeword size;
a second encoder of the plurality of encoders is operative to encode a second portion of the plurality of information bits thereby generating a second codeword having a second codeword size;
each of the plurality of memory depths, by which each of the plurality of encoders is operative to perform encoding, corresponds to a respective codeword size; and
based on the predetermined total memory depth, the processor selects the first codeword size and the second codeword size.

12. The apparatus of claim 1 , wherein:
the encoder is a variable code rate encoder that is operative to:
encode a first portion of the plurality of information bits in accordance with a first code rate thereby generating a first codeword; and
encode a second portion of the plurality of information bits in accordance with a second code rate thereby generating a second codeword having a second codeword size;

each of the plurality of memory depths, by which the variable code rate encoder is operative to perform encoding, corresponds to a respective code rate; and
based on the predetermined total memory depth, the processor selects the first code rate and the second code rate.

13. The apparatus of claim 1 , wherein:
during a first time, the encoder is operative to:
encode a first portion of the plurality of information bits using the maximum per signal memory depth thereby generating a first signal to be transmitted via a first service flow;
encode a second portion of the plurality of information bits using a memory depth that is less than the maximum per signal memory depth thereby generating a second signal to be transmitted via a second service flow; and

during a second time, the encoder is operative to:
encode a third portion of the plurality of information bits using the memory depth that is less than the maximum per signal memory depth thereby generating a third signal to be transmitted via the first service flow; and
encode a fourth portion of the plurality of information bits using the maximum per signal memory depth thereby generating a fourth signal to be transmitted via the second service flow.

14. The apparatus of claim 1 , wherein:
the apparatus is a communication device;
the communication device is coupled to a plurality of communication channels; and
each of the plurality of service flows is transmitted respectively via a corresponding one of the plurality of communication channels.

15. The

Assignees

• Kolze Thomas J
• Broadcom Corp

Inventors

• Kolze Thomas J

Classifications

• H03M13/6505

  Memory efficient implementations · CPC title

• H03M13/2732

  Convolutional interleaver; Interleavers using shift-registers or delay lines like, e.g. Ramsey type interleaver · CPC title

• H03M13/6516

  Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields · CPC title

• H03M13/1515

  Reed-Solomon codes · CPC title

• H03M13/6513 Primary

  Support of multiple code types, e.g. unified decoder for LDPC and turbo codes · CPC title