Memory controller operating method and memory controller

Patent metadata

Field	Value
Publication number	US-9524208-B2
Application number	US-201414322404-A
Country	US
Kind code	B2
Filing date	Jul 2, 2014
Priority date	Dec 24, 2013
Publication date	Dec 20, 2016
Grant date	Dec 20, 2016

Abstract

A method of operating a memory controller includes; receiving hard decision data and first soft decision data from a non-volatile memory device, performing a first ECC decoding operation using the hard decision data and the first soft decision data: and then determining a second soft decision read voltage or reclaim operation of the non-volatile memory device based on the number of iteration operation of the first ECC (error correction code).

First claim

What is claimed is:

1. A method of operating a memory controller, the method comprising:
receiving hard decision data and first soft decision data from a non-volatile memory device;
performing a plurality of iterations of a first error correction code (ECC) decoding operation using the hard decision data and the first soft decision data; and
determining a second soft decision read voltage or determining to perform a reclaim operation of the non-volatile memory device based on a number of iterations, the number of iterations indicating how many iterations of the first ECC decoding operation are included in the plurality of iterations.

2. The method of claim 1 , wherein the first ECC decoding operation uses iterative code.

3. The method of claim 2 , wherein the iterative code is LDPC (low density parity check) code.

4. The method of claim 1 , wherein the determining a second soft decision read voltage or determining to perform a reclaim operation includes performing the reclaim operation when the first ECC decoding operation succeeds and an error bit of the hard decision data is corrected.

5. The method of claim 1 , wherein the determining a second soft decision read voltage or determining to perform a reclaim operation includes determining the second soft decision read voltage when the first ECC decoding operation fails.

6. The method of claim 1 , further comprising:
performing a second ECC decoding operation using a second soft decision data read using the second soft decision read voltage.

7. The method of claim 1 , wherein the determining a second soft decision read voltage or determining to perform a reclaim operation includes determining the second soft decision read voltage by referring to a look up table indicating a correlation between the number of iterations and a ratio of strong error bits.

8. The method of claim 7 , wherein the referring to a look up table includes accessing a read only memory (ROM) storing the look up table.

9. The method of claim 1 , further comprising:
performing a first soft decision read operation to receive the first soft decision data, the first soft decision read operation being performed by using a soft decision offset.

10. A method of operating a memory controller, the method comprising:
performing a first soft decision read operation;
receiving hard decision data and first soft decision data from a non-volatile memory device, the first soft decision data being received as a result of the first soft decision read operation;
performing a plurality of iterations of a first error correction code (ECC) decoding operation using the hard decision data and the first soft decision data; and
determining, when the first ECC decoding operation fails, an offset of a second soft decision read operation subsequent to performing the first soft decision read operation,
the determining being based on a number of iterations, the number of iterations indicating how many iterations of the first ECC decoding operation are included in the plurality of iterations.

11. The method of claim 10 , wherein the first ECC decoding operation uses an iterative code.

12. The method of claim 11 , the iterative code is a low density parity check (LDPC) code.

13. The method of claim 10 , wherein the determining comprises:
determining the offset of the second soft decision read operation to have a first value when the number of iterations is bigger than a reference value; and
determining the offset of the second soft decision read operation to have a second value when the number of iterations is not bigger than the reference value, the first value being bigger than the second value.

14. The method of claim 10 , wherein the determining an offset includes determining the offset such that the absolute value of the offset is proportional to the number of iterations.

15. The method of claim 10 , wherein the offset determines a log likelihood ratio (LLR) of ECC decoding.

16. The method of claim 10 , wherein the determining an offset includes referring to a look up table indicating a correlation between the number of iteration operation and a ratio of strong error bits.

17. The method of claim 10 , further comprising:
performing the second soft decision read operation using the offset.

18. A method of operating a memory controller, the method comprising:
performing a hard decision reading operation by reading hard decision data from a nonvolatile memory device;
performing a first soft decision reading operation by reading first soft decision data from the nonvolatile memory device using a first soft decision reading voltage;
performing a first number of iterations of a first error correction code (ECC) decoding operation using the hard decision data and first soft decision data;
determining, at the memory controller, a second soft decision reading voltage based on the first number of iterations; and
performing a second soft decision reading operation by reading second soft decision data from the nonvolatile memory device using the determined second soft decision reading voltage.

19. The method of claim 18 , wherein determining, at the memory controller, a second soft decision reading voltage based on the first number of iterations comprises:
accessing a look up table (LUT) that indicates relationships between a plurality of numbers of iterations of the first ECC code decoding operation and corresponding ones of a plurality of ratio values, respectively;
determining, at the memory controller, a ratio value from among the plurality of ratio values that corresponds to the first number of iterations according to the LUT; and
determining the second soft decision reading voltage based on the ratio value that corresponds to the first number of iterations.

20. The method of claim 19 , wherein the ratio value is a ratio of a number of strong error bits to a total number of error bits in the first soft decision data, the strong error bits being bits associated with threshold values of memory cells of the nonvolatile memory device that result in read errors when read using a hard decision reading voltage and when read using the first soft decision reading voltage.

Assignees

• Kim Kyung-Jin
• Kim Ung-Hwan
• Kong Jun-Jin
• Kim Nam-Shik
• Samsung Electronics Co Ltd

Inventors

• Kim Kyung-Jin
• Kim Ung-Hwan
• Kong Jun-Jin
• Kim Nam-Shik

Classifications

• H03M13/458

  by updating bit probabilities or hard decisions in an iterative fashion for convergence to a final decoding result · CPC title

• H03M13/3707

  Adaptive decoding and hybrid decoding, e.g. decoding methods or techniques providing more than one decoding algorithm for one code · CPC title

• H03M13/1111

  Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms · CPC title

• G06F11/1068

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• H03M13/3927

  Log-Likelihood Ratio [LLR] computation by combination of forward and backward metrics into LLRs · CPC title