Method for forming interconnects

Patent metadata

Field	Value
Publication number	US-9378976-B2
Application number	US-201514677673-A
Country	US
Kind code	B2
Filing date	Apr 2, 2015
Priority date	Apr 2, 2014
Publication date	Jun 28, 2016
Grant date	Jun 28, 2016

Abstract

A conductive interconnect including trenches ( 110 ) and ( 186 ) and vias ( 202 ) are formed in a workpiece ( 100 ) by applying a dielectric film stack ( 120 ) over the workpiece, and thereafter applying photoresist ( 140 ) over the film stack. Trenches ( 142 ) are patterned in the photoresist, wherein the trenches are in segments disposed end-to-end to each other. The segments are longitudinally spaced apart from each other at locations where the vias ( 202 ) are to be located. The trenches are etched into the dielectric film stack, and then filled with conductive material to form metal line segments ( 186 ). Vias ( 192 ) are patterned in the gaps separating the adjacent ends of the longitudinally-related lines ( 186 ). The patterned vias are etched and then filled with a conductive material, with the ends of the adjacent line segments ( 186 ) serving to accurately locate the vias, in a direction along the lengths of the trenches.

First claim

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A method of forming an interconnect including trenches and vias in a workpiece, the method comprising:
applying a dielectric film stack on the workpiece;
applying a hard mask over the dielectric film stack;
applying a photoresist over the hard mask;
patterning trenches in the photoresist, the trenches being patterned in longitudinal segments disposed end-to-end to each other, the segments longitudinally spaced apart from each other at locations where vias are to be located;
etching trenches into the dielectric film stack;
filling the trenches with a conductive material;
patterning vias in the gaps separating the ends of longitudinally related filled trenches;
etching the patterned vias in the workpiece; and
filling the etched vias with the conductive material.

2. A method of forming an interconnect including trenches and vias in a workpiece, the method comprising:
applying a dielectric film stack on the workpiece;
applying a hard mask over the dielectric film stack;
applying a photoresist over the hard mask;
patterning vias in the photoresist defining gaps separating vias;
etching the patterned vias in the workpiece;
filling the etched vias with a conductive material;
patterning trenches in the photoresist, the trenches being patterned in longitudinal segments disposed end-to-end to each other in the gaps separating the vias, the segments longitudinally spaced apart from each other at the locations of the vias;
etching trenches into the dielectric film stack; and
filling the trenches with the conductive material.

3. A semiconductor workpiece comprising trenches and vias produced by:
applying a dielectric composition on the workpiece;
applying a hard mask over the dielectric composition;
applying a photoresist over the hard mask;
patterning trenches in the photoresist, the trenches being patterned in longitudinally arranged segments disposed end-to-end to each other, the longitudinal segments spaced apart from each other at locations where vias are to be located;
etching trenches into the dielectric composition;
filling the trenches with a conductive material;
patterning vias in the gaps separating the ends of longitudinally related trenches;
etching the patterned vias in the dielectric composition; and
filling the etched vias with the conductive material.

4. The workpiece of claim 3 , wherein, after formation of the trenches, the photoresist is applied over the trenches, and the vias are patterned on such photoresist.

5. The workpiece of claim 3 , wherein, after the etching of the vias, a barrier layer is deposited over the via sidewall surface.

6. The workpiece of claim 3 , wherein a metal overburden of the via fill material is applied to the workpiece.

7. The workpiece of claim 3 , further comprising removing the overburden to reduce the height of the workpiece to expose the conductive material filled trenches and aligned vias.

8. A semiconductor workpiece comprising trenches and vias produced by:
applying a dielectric film stack on the workpiece;
applying a hard mask over the dielectric film stack;
applying a photoresist over the hard mask;
patterning vias in the photoresist defining gaps separating the vias;
etching the patterned vias in the workpiece;
filling the etched vias with a conductive material;
patterning trenches in the photoresist, the trenches being patterned in longitudinal segments disposed end-to-end to each other in the gaps separating the vias, the segments longitudinally spaced apart from each other at the locations of the vias;
etching trenches into the dielectric film stack; and
filling the trenches with the conductive material.

Assignees

• Applied Materials Inc

Inventors

• Shaviv Roey

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10P14/47

  Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10P76/2041

  Photolithographic processes · CPC title

• H10P52/403

  of conductive or resistive materials · CPC title