Accumulator and data weighted average device including the accumulator

US9378184B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9378184-B2
Application numberUS-201313854041-A
CountryUS
Kind codeB2
Filing dateMar 29, 2013
Priority dateApr 10, 2012
Publication dateJun 28, 2016
Grant dateJun 28, 2016

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Abstract

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Disclosed are an accumulator for reducing nonlinearity of a data converter and a data weighted average device including the accumulator. According to the accumulator including a register configured to output input data according to a clock signal; a first adder configured to receive a digital input signal having any bit width and an output signal from the register to perform an add operation; a preset unit configured to output a preset value or a 0 value according to whether a carry of the first adder is generated; and a second adder configured to receive an output signal of the first adder and an output signal of the preset unit to perform the add operation and input the add operation to the register and the data weighted average device including the accumulator, it is possible to improve the nonlinearity occurring in the data converter by generating a number of DAC codes in addition to 2 n DAC codes.

First claim

Opening claim text (preview).

What is claimed is: 1. A data weighted average device, comprising: a data weighted average pointer circuit based on an accumulator configured to generate a pointer value corresponding to a digital input signal as a control signal; and a log shifter configured to perform path conversion of the digital input signal to an output signal according to the control signal output from the data weighted average pointer circuit based on the accumulator, wherein the data weighted average pointer circuit based on the accumulator includes: a thermometer binary converter configured to receive the digital input signal that has a bit width and is a thermometer code and convert the received digital input signal into an N bit binary code; and a modular M accumulator configured to use a preset value as a start value to count the N bit binary code into any natural number M value when a carry is generated as a result of a first add operation, the first add operation being performed to add the N bit binary code to a feedback signal, wherein the preset value is a difference value between 2 N and the M, N and M being natural numbers. 2. The data weighted average device of claim 1 , wherein the modular M accumulator includes: a register configured to output input data as the feedback signal according to a clock signal; a first adder configured to receive the N bit binary code and the feedback signal to perform the first add operation; a preset unit configured to output the preset value or a 0 value according to whether the carry is generated as the result of the first add operation; and a second adder configured to receive an output signal of the first adder and an output signal of the preset unit to perform a second add operation and input a result of the second add operation to the register. 3. The data weighted average device of claim 2 , wherein the preset unit includes: a first switch configured to be turned on when the carry is generated to output the preset value to the second adder; and a second switch configured to be turned on when the carry is not generated to output the 0 value to the second adder. 4. The data weighted average device of claim 1 , wherein the any natural number M is a natural number other than 2 N .

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Classifications

  • Details of the digital/analogue conversion in the feedback path · CPC title

  • with intermediate conversion to phase of sinusoidal or similar periodical signals · CPC title

  • G06F17/10Primary

    Complex mathematical operations {(function generation by table look-up G06F1/03; evaluation of elementary functions by calculation G06F7/544)} · CPC title

  • G06F7/50Primary

    Adding; Subtracting (G06F7/483 - G06F7/491, G06F7/544 - G06F7/556 take precedence) · CPC title

  • H03M1/0665Primary

    using data dependent selection of the elements, e.g. data weighted averaging · CPC title

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What does patent US9378184B2 cover?
Disclosed are an accumulator for reducing nonlinearity of a data converter and a data weighted average device including the accumulator. According to the accumulator including a register configured to output input data according to a clock signal; a first adder configured to receive a digital input signal having any bit width and an output signal from the register to perform an add operation; a…
Who is the assignee on this patent?
Korea Electronics Telecomm
What technology area does this patent fall under?
Primary CPC classification G06F17/10. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jun 28 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).