Apparatus and method for cyclic redundancy check
US-2016371142-A1 · Dec 22, 2016 · US
Composite finite field multiplier
US9201847B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9201847-B2 |
| Application number | US-201214123761-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 25, 2012 |
| Priority date | Sep 9, 2011 |
| Publication date | Dec 1, 2015 |
| Grant date | Dec 1, 2015 |
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Abstract
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A composite finite field multiplier is disclosed. The multiplier includes a controller, an input port, an output port, a GF((2 n ) 2 ) multiplier, a GF(2 n ) standard basis multiplier, and a GF(2 n ) look-up table multiplier; the controller is connected respectively to the input port, the output port, the GF((2 n ) 2 ) multiplier, the GF(2 n ) standard basis multiplier and the GF(2 n ) look-up table multiplier; the GF((2 n ) 2 ) multiplier is connected respectively to the GF(2 n ) standard basis multiplier and the GF(2 n ) look-up table multiplier. By using the GF((2 n ) 2 ) multiplier, the GF(2 n ) standard basis multiplier and the GF(2 n ) look-up table multiplier, the multiplication of three operands is realized. Compared with the existing multiplier, the multiplier of the present invention has significant advantages in the speed of multiplying three operands over GF((2 n ) m ).
First claim
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What is claimed is: 1. A composite finite field multiplier, comprising: an input port, configured to input an operand a(x), an operand b(x), an operand c(x), an irreducible polynomial p(x) selected over the GF(2 n ) field, an irreducible polynomial q(x) selected over the GF((2 n ) m ) field and a control signal k; a GF(2 n ) standard basis multiplier, configured to implement the multiplication (a(x)×b(x)×c(x))mod(p(x)) of the three operands a(x), b(x) and c(x) on the standard b…
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- What does patent US9201847B2 cover?
- A composite finite field multiplier is disclosed. The multiplier includes a controller, an input port, an output port, a GF((2 n ) 2 ) multiplier, a GF(2 n ) standard basis multiplier, and a GF(2 n ) look-up table multiplier; the controller is connected respectively to the input port, the output port, the GF((2 n ) 2 ) multiplier, the GF(2 n ) standard basis multiplier and the GF(2 n ) look-up …
- Who is the assignee on this patent?
- Tang Shaohua, Yi Haibo, Univ South China Tech
- What technology area does this patent fall under?
- Primary CPC classification G06F7/724. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Dec 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).