Film portion at wafer edge

US9372406B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9372406-B2
Application numberUS-201313764155-A
CountryUS
Kind codeB2
Filing dateFeb 11, 2013
Priority dateApr 13, 2012
Publication dateJun 21, 2016
Grant dateJun 21, 2016

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A film layer on a substrate of the wafer is patterned to form a first plurality of areas of the film layer and a second plurality of areas of the film layer. The first plurality of areas of the film layer is removed. The second plurality of areas of the film layer is kept on the substrate. A first portion of the film layer is kept on the substrate. A first edge of the first portion of the film layer is substantially near an edge of the wafer. The first portion of the film layer defines a boundary for the wafer.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for preparing a wafer, comprising: patterning a film layer on the wafer to form an annular portion of the film layer and a circular portion of the film layer, the circular portion contained within the annular portion, the circular portion having a plurality of patterned features therein; keeping the circular portion of the film layer on the wafer; keeping the annular portion of the film layer on the wafer; and removing portions of the plurality of patterned features of the film layer from within the circular portion, wherein the annular portion and the wafer directly thereunder are free from having patterned features; a first edge of the annular portion is substantially near an edge of the wafer; and the first edge of the annular portion of the film layer defines a boundary for the wafer. 2. The method of claim 1 , wherein removing the portions of the plurality of patterned features areas of the film layer from within the circular portion comprises etching. 3. The method of claim 1 , wherein patterning the film layer comprises coating the film layer with a negative photoresist layer; performing a wafer edge exposure (WEE) process on a portion of the negative photoresist layer that corresponds to the annular portion of the film layer; patterning a portion of the negative photoresist layer corresponding to the circular portion of the film layer to form a plurality of areas of the negative photoresist layer therein. 4. The method of claim 3 , further comprising removing an unexposed plurality of areas of the negative photoresist layer from the circular portion before removing the first plurality of areas of the film layer; and removing the portion of the negative photoresist layer corresponding to the annular portion of the film layer after removing the plurality of areas of the film layer. 5. The method of claim 3 , wherein patterning the negative photoresist layer corresponding to the circular portion of the film layer comprises: using a mask and an energy source to form the plurality of areas of the negative photoresist layer; or using a nano-imprint process; or using a direct e-beam writing process. 6. The method of claim 5 , wherein the energy source is selected from the group consisting of a light and an electron beam. 7. The method of claim 1 , wherein patterning the film layer comprises: having a first negative photoresist portion and a second negative photoresist portion on top of the film layer; removing the second negative photoresist portion, thereby exposing a portion of the film layer; coating a positive photoresist layer over the exposed portion of the film layer and the first negative photoresist portion; and patterning the positive photoresist layer to form a first plurality of areas of the positive photoresist layer and a second plurality of areas of the positive resist layer, wherein the first plurality of areas of the positive photo resist layer corresponds to the first plurality of areas of the film layer and the second plurality of areas of the positive resist layer corresponds to the second plurality of areas of the film layer. 8. The method of claim 7 , wherein patterning the positive photoresist layer comprises: using a mask and an energy source; and removing the first plurality of areas of the positive photoresist layer, wherein the first plurality of areas of the positive photoresist layer is exposed to the energy source through the mask and the second plurality of areas of the positive photoresist layer is not exposed through mask; or using a nano-imprint process; or using a direct e-beam writing with the negative photoresist layer. 9. The method of claim 8 , wherein the energy source is selected from the group consisting of a light and an electron beam. 10. The method of claim 7 , further comprising: performing a wafer edge exposure process on a portion of the positive photoresist layer corresponding to the first negative photoresist portion. 11. The method of claim 7 , further comprising: removing the first plurality of areas of the positive photoresist layer before removing the first plurality of areas of the film layer; and removing the second plurality of areas of the positive photoresist layer after removing the first plurality of areas of the film layer. 12. The method of claim 7 , wherein the first negative photoresist portion and the second negative photoresist portion are part of a negative photoresist layer coated over the film layer; and the first negative photoresist portion is subject to a wafer edge exposure process prior to removing the second negative photoresist portion. 13. The method of claim 1 , wherein patterning the film layer comprises coating the film layer with a positive photoresist layer; performing a wafer edge exposure process on a first portion of the positive photoresist layer, wherein the first portion of the positive photoresist layer corresponds to the first portion of the film layer; and patterning the positive photoresist layer, to form a first plurality of areas of the positive photoresist layer and a second plurality of areas of the positive resist layer, wherein the first plurality of areas of the positive photoresist layer corresponds to the first plurality of areas of the film layer and the second plurality of areas of the positive photoresist layer corresponds to the second plurality of areas of the film layer; and performing the wafer edge exposure process on the first portion of the positive photoresist layer using at least one of an energy level between 30 and 60 mJ/cm 2 , an energy level of at least 60 mJ/cm 2 , or a light having a wavelength of about 248 nm. 14. The method of claim 13 , wherein patterning the positive photoresist layer comprises: using a mask and an energy source; and removing the first plurality of areas of the positive photoresist layer, wherein the first plurality of areas of the positive photoresist layer is exposed to the energy source through the mask; or using a nano-imprint process; or using a direct e-beam writing with the negative photoresist layer. 15. The method of claim 14 , wherein the energy source is selected from the group consisting of a light and an electron beam. 16. The method of claim 13 , further comprising: removing the first plurality of areas of the positive photoresist layer before removing the first plurality of areas of the film layer; and removing the second plurality of areas of the positive photoresist layer after removing the first plurality of areas of the film layer. 17. A method comprising: coating a film layer with a negative photoresist layer, wherein the film layer is underlying the negative photoresist layer and overlying a wafer; performing a wafer edge exposure (WEE) process on a portion of the negative photoresist layer, wherein the exposed portion of the negative photoresist layer corresponds to an annular portion of the underlying film layer, wherein an outer edge of the exposed portion of the negative photoresist layer is substantially near an edge of the wafer and an inner edge of the exposed portion of the negative photoresist layer defines an outer edge of an unexposed, circular portion of the negative photoresist layer corresponding to a circular portion of the underlying film layer; exposing the circular portion of the negative photoresist layer to form patterns therein after the WEE proceess; removing first negative photoresist portions from the patterned circular portion of the negative photoresist layer to form openings therei

Assignees

Inventors

Classifications

  • Planarisation of organic insulating materials · CPC title

  • Photolithographic processes · CPC title

  • characterised by their behaviour during the process, e.g. soluble masks or redeposited masks · CPC title

  • using masks for insulating materials · CPC title

  • Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9372406B2 cover?
A film layer on a substrate of the wafer is patterned to form a first plurality of areas of the film layer and a second plurality of areas of the film layer. The first plurality of areas of the film layer is removed. The second plurality of areas of the film layer is kept on the substrate. A first portion of the film layer is kept on the substrate. A first edge of the first portion of the film …
Who is the assignee on this patent?
Taiwan Semiconductor Mfg
What technology area does this patent fall under?
Primary CPC classification H10P76/2041. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jun 21 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).